Before I go too far down this path, I figured I should just ask the question...

The SDCLK<0> output pin on the PXA270 is wired to SA_SDCLK0, which is
wired to pin Y11 on the FPGA.  I would like to run some synchronous
logic (specifically, a dual clocked FIFO) off of this clock.  Right
now, it doesn't seem to be wiggling.  I can think of 2 reasons
immediately why I might not see it wiggling:

1) I did something wrong.

2) It doesn't wiggle unless it is configured to do so, and the default
kernel doesn't configure it to wiggle.

I'm working on trying to figure out option (1).  I thought I should
ask you folks about option (2).

--wpd