From subversion@balloonboard.org Sun May 11 02:24:34 2008 Received: from localhost ([127.0.0.1] helo=localhost.localdomain) by stoneboat.aleph1.co.uk with esmtp (Exim 4.63) (envelope-from ) id 1Jv0Ij-0005z9-88 for balloon-svn@balloonboard.org; Sun, 11 May 2008 02:24:33 +0100 To: balloon-svn@balloonboard.org From: subversion@balloonboard.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-Id: Date: Sun, 11 May 2008 02:24:33 +0100 X-SA-Exim-Connect-IP: 127.0.0.1 X-SA-Exim-Mail-From: subversion@balloonboard.org X-SA-Exim-Scanned: No (on stoneboat.aleph1.co.uk); SAEximRunCond expanded to false Subject: [Balloon-svn] r479 - in balloon/trunk: initrd kernel kernel/2.6.25.2 X-BeenThere: balloon-svn@balloonboard.org X-Mailman-Version: 2.1.9 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 11 May 2008 01:24:34 -0000 Author: wookey Date: 2008-05-11 02:24:31 +0100 (Sun, 11 May 2008) New Revision: 479 Added: balloon/trunk/initrd/initrdmodules-2.6.25.2.list balloon/trunk/kernel/2.6.25.2/ balloon/trunk/kernel/2.6.25.2/balloon3-ethernet.patch balloon/trunk/kernel/2.6.25.2/balloon3-leds.patch balloon/trunk/kernel/2.6.25.2/balloon3-minipug.patch balloon/trunk/kernel/2.6.25.2/balloon3-nand.patch balloon/trunk/kernel/2.6.25.2/balloon3-pcmcia.patch balloon/trunk/kernel/2.6.25.2/balloon3-samosa.patch balloon/trunk/kernel/2.6.25.2/balloon3-vga.patch balloon/trunk/kernel/2.6.25.2/balloon3.patch balloon/trunk/kernel/2.6.25.2/balloon3config-add-wlan-modules.patch balloon/trunk/kernel/2.6.25.2/balloon3config.patch balloon/trunk/kernel/2.6.25.2/balloon3configEABI.patch balloon/trunk/kernel/2.6.25.2/fixups.patch balloon/trunk/kernel/2.6.25.2/initrd.patch balloon/trunk/kernel/2.6.25.2/pxa-fixups.patch balloon/trunk/kernel/2.6.25.2/pxa27x_udc.patch balloon/trunk/kernel/2.6.25.2/series balloon/trunk/kernel/2.6.25.2/series.arm-linux-gnu- balloon/trunk/kernel/2.6.25.2/series.arm-linux-gnueabi- balloon/trunk/kernel/2.6.25.2/yaffs-2.6.25.patch balloon/trunk/kernel/2.6.25.2/yaffsconfig.patch Log: Add port-forward to kernel 2.6.25.2 inlcudes re-writen pxa27x_udc driver Added: balloon/trunk/initrd/initrdmodules-2.6.25.2.list =================================================================== --- balloon/trunk/initrd/initrdmodules-2.6.25.2.list (rev 0) +++ balloon/trunk/initrd/initrdmodules-2.6.25.2.list 2008-05-11 01:24:31 UTC (rev 479) @@ -0,0 +1,50 @@ +fs/ext2/ext2.ko +fs/fat/fat.ko +fs/vfat/vfat.ko +drivers/usb/host/ohci-hcd.ko +drivers/scsi/sd_mod.ko +drivers/scsi/scsi_mod.ko +drivers/usb/storage/usb-storage.ko +fs/nls/nls_cp437.ko +fs/nls/nls_cp850.ko +fs/nls/nls_cp858.ko +fs/nls/nls_cp1250.ko +fs/nls/nls_iso8859-1.ko +fs/nls/nls_iso8859-2.ko +fs/nls/nls_iso8859-3.ko +fs/nls/nls_iso8859-4.ko +fs/nls/nls_iso8859-5.ko +fs/nls/nls_iso8859-6.ko +fs/nls/nls_iso8859-7.ko +fs/nls/nls_iso8859-9.ko +fs/nls/nls_iso8859-13.ko +fs/nls/nls_iso8859-14.ko +fs/nls/nls_iso8859-15.ko +fs/nls/nls_utf8.ko +drivers/usb/storage/libusual.ko +drivers/leds/led-class.ko +drivers/ide/ide-core.ko +drivers/usb/gadget/pxa27x_udc.ko +drivers/usb/gadget/g_ether.ko +drivers/usb/gadget/g_serial.ko +drivers/net/usb/usbnet.ko +drivers/usb/core/usbcore.ko +drivers/net/mii.ko +drivers/net/usb/pegasus.ko +drivers/net/usb/asix.ko +drivers/net/usb/dm9601.ko +drivers/pcmcia/pxa2xx_cs.ko +drivers/pcmcia/pxa2xx_core.ko +drivers/pcmcia/pcmcia.ko +drivers/pcmcia/pcmcia_core.ko +drivers/net/wireless/libertas/libertas.ko +drivers/net/wireless/libertas/libertas_cs.ko +drivers/net/wireless/libertas/usb8xxx.ko +drivers/net/wireless/hostap/hostap.ko +drivers/net/wireless/hostap/hostap_cs.ko +net/ieee80211/ieee80211_crypt.ko +net/ieee80211/ieee80211.ko +drivers/rtc/rtc-sa1100.ko +drivers/rtc/rtc-core.ko +drivers/mmc/host/pxamci.ko +drivers/mmc/core/mmc_core.ko Added: balloon/trunk/kernel/2.6.25.2/balloon3-ethernet.patch =================================================================== --- balloon/trunk/kernel/2.6.25.2/balloon3-ethernet.patch (rev 0) +++ balloon/trunk/kernel/2.6.25.2/balloon3-ethernet.patch 2008-05-11 01:24:31 UTC (rev 479) @@ -0,0 +1,13 @@ +Index: linux-2.6.25.2/drivers/net/Kconfig +=================================================================== +--- linux-2.6.25.2.orig/drivers/net/Kconfig 2008-05-07 00:21:32.000000000 +0100 ++++ linux-2.6.25.2/drivers/net/Kconfig 2008-05-09 16:49:06.000000000 +0100 +@@ -1417,7 +1417,7 @@ + + config CS89x0 + tristate "CS89x0 support" +- depends on NET_PCI && (ISA || MACH_IXDP2351 || ARCH_IXDP2X01 || ARCH_PNX010X) ++ depends on NET_PCI && (ISA || MACH_IXDP2351 || ARCH_IXDP2X01 || ARCH_PNX010X || MACH_BALLOON3) + ---help--- + Support for CS89x0 chipset based Ethernet cards. If you have a + network (Ethernet) card of this type, say Y and read the Added: balloon/trunk/kernel/2.6.25.2/balloon3-leds.patch =================================================================== --- balloon/trunk/kernel/2.6.25.2/balloon3-leds.patch (rev 0) +++ balloon/trunk/kernel/2.6.25.2/balloon3-leds.patch 2008-05-11 01:24:31 UTC (rev 479) @@ -0,0 +1,153 @@ +Index: arch/arm/mach-pxa/Makefile +=================================================================== +--- arch/arm/mach-pxa/Makefile.orig 2008-05-09 15:09:59.000000000 +0100 ++++ arch/arm/mach-pxa/Makefile 2008-05-09 15:11:14.000000000 +0100 +@@ -43,6 +43,7 @@ + led-y := leds.o + led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o + led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o ++led-$(CONFIG_MACH_BALLOON3) += leds-balloon3.o + led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o + led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o + +Index: arch/arm/mach-pxa/leds-balloon3.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ arch/arm/mach-pxa/leds-balloon3.c 2008-05-09 15:10:22.000000000 +0100 +@@ -0,0 +1,113 @@ ++/* ++ * linux/arch/arm/mach-pxa/leds-balloon3.c ++ * ++ * Author: Nicolas Pitre ++ * Created: Nov 05, 2002 ++ * Copyright: MontaVista Software Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "leds.h" ++ ++ ++#define LED_STATE_ENABLED 1 ++#define LED_STATE_CLAIMED 2 ++ ++static unsigned int led_state; ++static char flipflop; ++ ++void balloon3_leds_event(led_event_t evt) ++{ ++ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ ++ switch (evt) { ++ ++ case led_start: ++ led_state = LED_STATE_ENABLED; ++ break; ++ ++ case led_stop: ++ led_state &= ~LED_STATE_ENABLED; ++ break; ++ ++ case led_claim: ++ led_state |= LED_STATE_CLAIMED; ++ break; ++ ++ case led_release: ++ led_state &= ~LED_STATE_CLAIMED; ++ break; ++ ++#ifdef CONFIG_LEDS_TIMER ++ case led_timer: ++ if (led_state & LED_STATE_ENABLED) { ++ flipflop = !flipflop; ++ if (flipflop) ++ GPSR(BALLOON3_GPIO_LED_TIMER) = GPIO_bit(BALLOON3_GPIO_LED_TIMER); ++ else ++ GPCR(BALLOON3_GPIO_LED_TIMER) = GPIO_bit(BALLOON3_GPIO_LED_TIMER); ++ } ++ break; ++#endif ++ ++#ifdef CONFIG_LEDS_CPU ++ case led_idle_start: ++ if (led_state & LED_STATE_ENABLED) ++ GPCR(BALLOON3_GPIO_LED_IDLE) = ! GPIO_bit(BALLOON3_GPIO_LED_IDLE); ++ break; ++ ++ case led_idle_end: ++ if (led_state & LED_STATE_ENABLED) ++ GPSR(BALLOON3_GPIO_LED_IDLE) = ! GPIO_bit(BALLOON3_GPIO_LED_IDLE); ++ break; ++#endif ++ ++ case led_halted: ++ break; ++ ++ case led_green_on: ++// hw_led_state |= D21;; ++ break; ++ ++ case led_green_off: ++// hw_led_state &= ~D21; ++ break; ++ ++ case led_amber_on: ++// hw_led_state |= D22;; ++ break; ++ ++ case led_amber_off: ++// hw_led_state &= ~D22; ++ break; ++ ++ case led_red_on: ++// hw_led_state |= D23;; ++ break; ++ ++ case led_red_off: ++// hw_led_state &= ~D23; ++ break; ++ default: ++ break; ++ } ++ ++ ++ local_irq_restore(flags); ++} +Index: arch/arm/mach-pxa/leds.h +=================================================================== +--- arch/arm/mach-pxa/leds.h.orig 2008-05-07 00:21:32.000000000 +0100 ++++ arch/arm/mach-pxa/leds.h 2008-05-09 15:10:22.000000000 +0100 +@@ -10,4 +10,5 @@ + extern void idp_leds_event(led_event_t evt); + extern void lubbock_leds_event(led_event_t evt); + extern void mainstone_leds_event(led_event_t evt); ++extern void balloon3_leds_event(led_event_t evt); + extern void trizeps4_leds_event(led_event_t evt); +Index: arch/arm/mach-pxa/leds.c +=================================================================== +--- arch/arm/mach-pxa/leds.c.orig 2008-05-07 00:21:32.000000000 +0100 ++++ arch/arm/mach-pxa/leds.c 2008-05-09 15:10:22.000000000 +0100 +@@ -26,6 +26,8 @@ + leds_event = idp_leds_event; + if (machine_is_trizeps4()) + leds_event = trizeps4_leds_event; ++ if (machine_is_balloon3()) ++ leds_event = balloon3_leds_event; + + leds_event(led_start); + return 0; Added: balloon/trunk/kernel/2.6.25.2/balloon3-minipug.patch =================================================================== --- balloon/trunk/kernel/2.6.25.2/balloon3-minipug.patch (rev 0) +++ balloon/trunk/kernel/2.6.25.2/balloon3-minipug.patch 2008-05-11 01:24:31 UTC (rev 479) @@ -0,0 +1,772 @@ +Index: linux-2.6.25.2/drivers/char/Kconfig +=================================================================== +--- linux-2.6.25.2.orig/drivers/char/Kconfig 2008-05-09 15:10:03.000000000 +0100 ++++ linux-2.6.25.2/drivers/char/Kconfig 2008-05-09 16:49:34.000000000 +0100 +@@ -1058,6 +1058,12 @@ + Balloon2, 8 or 16 bit on Balloon3. You normally want this + unless you are using the bus lines for something else. + ++config MINIPUG ++ tristate "Minipug LCD display" ++ depends on SAMOSA ++ default y ++ help ++ 456*80 LCD display driven down Samosa bus (for Balloonboard). + + endmenu + +Index: linux-2.6.25.2/drivers/char/Makefile +=================================================================== +--- linux-2.6.25.2.orig/drivers/char/Makefile 2008-05-09 15:10:03.000000000 +0100 ++++ linux-2.6.25.2/drivers/char/Makefile 2008-05-09 16:49:34.000000000 +0100 +@@ -113,6 +113,7 @@ + js-rtc-y = rtc.o + + obj-$(CONFIG_SAMOSA) += samosa.o ++obj-$(CONFIG_MINIPUG) += minipug.o + + # Files generated that shall be removed upon make clean + clean-files := consolemap_deftbl.c defkeymap.c +Index: linux-2.6.25.2/drivers/char/minipug.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-2.6.25.2/drivers/char/minipug.c 2008-05-09 16:49:34.000000000 +0100 +@@ -0,0 +1,738 @@ ++/* ++ * linux/drivers/char/minipug.c ++ * ++ * file interface for minipug displays on the balloon samosa bus ++ * Copyright (c) N C Bane 2005 2006 for Toby Churchill Ltd ++ * ++*/ ++ ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_MACH_BALLOON2) ++#include ++//#include ++#endif ++#if defined(CONFIG_MACH_BALLOON3) ++#include ++#endif ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "linux/cdev.h" ++#include "samosa.h" ++ ++// uncomment to use a minipug class model. ++// This is needed at the moment for udev as ++// the add uevent seems to be missing the MAJOR ++// and MINOR fields if done via platform devices. ++//#define MINIPUG_CLASS ++#define SAMOSA_CLASS ++ ++// uncomment for fixed node major numbering ++// #define MINIPUG_MAJOR 200 ++ ++#ifdef MINIPUG_MAJOR ++static int major = MINIPUG_MAJOR; ++#else ++static int major = 0; ++module_param(major, int, 0); ++MODULE_PARM_DESC(major, "Major device number"); ++#endif ++ ++static spinlock_t minipug_lock; ++ ++#define dprintk(x...) ++ ++// total minipug on board ram ++#define BUFFER_SIZE (32*1024) ++ ++/* per device info */ ++ ++struct minipug_info { ++ unsigned int display; ++ unsigned char *buffer; ++ unsigned char bpp; ++}; ++ ++/* minipug i/o */ ++ ++static int active_display=0; ++//static inline unsigned char minipug_ready(int display) { return balloon_samosa_read8(CPLD_LCD_RO_SET) & ( 1<< (display ? CPLD_LCD_RO_LCD1_nWAIT_BIT : CPLD_LCD_RO_LCD0_nWAIT_BIT)); } ++unsigned char minipug_ready(int display) ++{ ++ unsigned char ret; ++ ret = (unsigned char) balloon_samosa_read8(CPLD_LCD_RO_SET) & ( 1<< (display ? CPLD_LCD_RO_LCD1_nWAIT_BIT : CPLD_LCD_RO_LCD0_nWAIT_BIT)); ++ printk (KERN_DEBUG "%s:returns %x\n",__FUNCTION__,ret); ++ return ret; ++ } ++ ++//bool displayWaiting(void) { return ((samosa_read(9) & (1<> 8) &0xff); ++} ++ ++static inline unsigned short Do_Read_Cursor_Address(void) ++ { ++ unsigned char lsb; ++ Write_Command(COMMAND_CSRR); ++ lsb=Read_Parameter(); ++ return ((Read_Parameter() << 8) &0xff ) | lsb; ++} ++ ++static void Do_Grayscale(int BPPSR) { ++ Write_Command(COMMAND_GRAYSCALE); ++ Write_Parameter(BPPSR); ++} ++ ++static inline void Do_Write_Memory_Byte(int b) { ++ Write_Command(COMMAND_MEMWRITE); ++ Write_Parameter(b); ++} ++ ++static inline unsigned char Do_Read_Memory_Byte(void) ++ { ++ Write_Command(COMMAND_MEMREAD); ++ return Read_Parameter(); ++} ++ ++static inline void Do_Write_Memory_Block(int count, unsigned char b) { ++ Write_Command(COMMAND_MEMWRITE); ++ Write_Parameter_Repeat(b,count); ++} ++ ++static void Do_Set_Addresses(int graphicspage, unsigned int bpp) { ++ // text layer ++ unsigned char SB1SAR0=TEXT_PAGE_START_ADDR & 0xff; ++ unsigned char SB1SAR1=(TEXT_PAGE_START_ADDR >> 8)&0xff; ++ unsigned char SB1SR=DISPLAY_HEIGHT; ++ ++ int SB2SAR0,SB2SAR1; ++ int SB2SR=DISPLAY_HEIGHT; ++ // graphics layer, can be one of two ++ // for double-buffering ++ if (graphicspage==0) { ++ SB2SAR0=GRAPHICS_PAGE_0_START_ADDR & 0xff; ++ SB2SAR1=(GRAPHICS_PAGE_0_START_ADDR >> 8) &0xff; ++ } ++ else { ++ SB2SAR0=GRAPHICS_PAGE_1_START_ADDR(bpp) & 0xff; ++ SB2SAR1=(GRAPHICS_PAGE_1_START_ADDR(bpp) >> 8) & 0xff; ++ } ++ // layers 3 and 4 are fixed cos we don't use them ++ Do_Scroll(SB1SAR0,SB1SAR1,SB1SR,SB2SAR0,SB2SAR1,SB2SR,0x00,0x00,0x00,0x30); ++} ++ ++static int minipug_guts_init(int useRamCharset, unsigned int bpp) { ++ ++ // dunno why this convoluted sequence is necessary but .... ++ Do_System_Set((useRamCharset ? 0x35:0x34),0x07,DISPLAY_LINES_PER_CHAR-1,DISPLAY_ADDRESSES_PER_LINE(bpp)-1,DISPLAY_ADDRESSES_PER_LINE(bpp)+DISPLAY_HSYNC_WIDTH,DISPLAY_HEIGHT,DISPLAY_ADDRESSES_PER_LINE(bpp),0); ++ Wait(20); ++ Do_System_Set((useRamCharset ? 0x35:0x34),0x07,DISPLAY_LINES_PER_CHAR-1,DISPLAY_ADDRESSES_PER_LINE(bpp)-1,DISPLAY_ADDRESSES_PER_LINE(bpp)+DISPLAY_HSYNC_WIDTH,DISPLAY_HEIGHT,DISPLAY_ADDRESSES_PER_LINE(bpp),0); ++ // scroll ++ // memory layout, selecting graphics page 0 ++ Do_Set_Addresses(0,bpp); ++ // hdot scr set to zero ++ Do_Hdot_Scroll(0); ++ // ovlay (OR superposition, first and third blocks text mode) ++ Do_Overlay(0x00); ++ // grayscale mode ++ if (bpp==1) ++ Do_Grayscale(0); ++ else if (bpp==2) ++ Do_Grayscale(1); ++ else if (bpp==4) ++ Do_Grayscale(2); ++ ++ // load character set ++// PRINT("Loading character set\n"); ++// Load_Character_set("/boot/minipug.charset"); ++ ++ // disp off ++ Do_Display_Off(0x57); ++ ++ // clear second memory layer (graphics) ++// PRINT("Clearing graphics\n"); ++ Select_Graphics_Page_Write(0,bpp); ++ Do_Write_Memory_Block(DISPLAY_HEIGHT*DISPLAY_ADDRESSES_PER_LINE(bpp),0); ++ // clear the third memory layer ++ Select_Graphics_Page_Write(1,bpp); ++ Do_Write_Memory_Block(DISPLAY_HEIGHT*DISPLAY_ADDRESSES_PER_LINE(bpp),0); ++ // clear first memory layer (text) ++// PRINT("Clearing text\n"); ++// Do_Write_Cursor_Address(0,0); ++ Do_Write_Cursor_Address(0); ++ Do_Write_Memory_Block(DISPLAY_HEIGHT_CHARS*DISPLAY_ADDRESSES_PER_LINE(bpp),32); ++ // csrw (set cursor to start of first screen block) ++// Do_Write_Cursor_Address(0,0); ++ Do_Write_Cursor_Address(0); ++ // csrform (5x7 or 5x14 pixel block cursor) ++// Do_Cursor_Format(0x04,0x86); ++ Do_Cursor_Format(0x04,useRamCharset ? 0x8d:0x86); ++ // disp on (same DAR as above) ++ Do_Display_On(0x57); ++ ++ return 0; ++} ++ ++static void update_graphics(unsigned char *data, unsigned int len, unsigned int offset) { ++ size_t graphics_address=GRAPHICS_PAGE_0_START_ADDR+offset; ++ // keep caches coherent by flushing. ++// lock ++ spin_lock(&minipug_lock); ++ ++ // this needs optimising if possible to only the mmaped aliases for this page. ++ flush_cache_all(); ++// flush_dcache_range((unsigned long)data+offset, (unsigned long)data+offset+len); ++// flush_icache_range((unsigned long)data, (unsigned long)data+len); ++ Do_Write_Cursor_Address(graphics_address); ++ Write_Command(COMMAND_MEMWRITE); ++ while (len--) ++ Write_Parameter(*(data++)); ++ ++ spin_unlock(&minipug_lock); ++// unlock ++//printk("%s: updated %d\n",__FUNCTION__,len); ++} ++ ++/* end low level minipug i/o */ ++ ++ssize_t minipug_read(struct file *, char *, size_t, loff_t *); ++ssize_t minipug_write(struct file *, const char *, size_t, loff_t *); ++int minipug_open(struct inode *, struct file *); ++int minipug_release(struct inode *, struct file *); ++int minipug_ioctl(struct inode *, struct file *, unsigned int, unsigned long); ++int minipug_mmap(struct file *, struct vm_area_struct *vm); ++ ++static struct file_operations minipug_fops = { ++ read: minipug_read, ++ write: minipug_write, ++ open: minipug_open, ++ release: minipug_release, ++ ioctl: minipug_ioctl, ++ mmap: minipug_mmap, ++}; ++ ++ ++struct minipug_info minipug[2]={ ++ {display: 0}, ++ {display: 1}, ++}; ++ ++/* proc interface */ ++static ssize_t proc_read_minipug(struct file * file, char * buf, ++ size_t nbytes, loff_t *ppos); ++static ssize_t proc_write_minipug(struct file * file, const char * buffer, ++ size_t count, loff_t *ppos); ++ ++static struct file_operations proc_minipug_operations = { ++ read: proc_read_minipug, ++ write: proc_write_minipug ++}; ++static struct proc_dir_entry *proc_minipug; ++#define PROC_MINIPUG "minipug" ++ ++static void minipug_setup(void) { ++ int disp=active_display ? 1:0; ++ minipug_guts_init(0,minipug[disp].bpp); ++ memset(minipug[disp].buffer,0,BUFFER_SIZE); ++ update_graphics(minipug[disp].buffer,BUFFER_SIZE,0); ++} ++ ++int minipug_open(struct inode *inode, struct file *filp) ++{ ++#ifndef CONFIG_BALLOON2_BUILD_TCL_PIKEY2 ++ if (balloon_samosa_sm_present()) ++ return -ENODEV; ++#endif ++ filp->private_data = &minipug[0]; ++printk("%s: opened\n",__FUNCTION__); ++ return 0; ++} ++ ++int minipug_release(struct inode *inode, struct file *filp) ++{ ++printk("%s: released\n",__FUNCTION__); ++ return 0; ++} ++ ++ssize_t minipug_read(struct file *filp, char * buf, ++ size_t size, loff_t *offp) ++{ ++ struct minipug_info *mp= (struct minipug_info *)filp->private_data; ++ if (*offp>=BUFFER_SIZE-1) ++ return -EINVAL; ++ if (*offp+size>BUFFER_SIZE) ++ size=BUFFER_SIZE-*offp; ++printk("%s: reading\n",__FUNCTION__); ++ return copy_to_user(buf,&mp->buffer[*offp],size); ++} ++ ++ssize_t minipug_write(struct file *filp, const char *buf, ++ size_t size, loff_t *offp) ++{ ++ struct minipug_info *mp= (struct minipug_info *)filp->private_data; ++ active_display=mp->display; ++ // first BUFFER_SIZE address spaces are the frame buffer ++ if (*offpBUFFER_SIZE) ++ size=BUFFER_SIZE-*offp; ++ copied = copy_from_user(&mp->buffer[*offp],buf,size); ++ update_graphics(mp->buffer+*offp,copied,*offp); ++ return copied; ++ } ++ else if (size == sizeof(unsigned int)) { ++ loff_t command=(*offp)-BUFFER_SIZE; ++ unsigned int arg; ++ unsigned long copied = copy_from_user(&arg,buf,sizeof(arg)); ++ if (command==0) { ++ if ((arg==1) || (arg==2) || (arg==4)) { ++ mp->bpp=arg; ++ minipug_setup(); ++ } ++ } ++#if 0 ++ switch ((*offp)-BUFFER_SIZE) { ++ case 0 : if ((cmd==1) || (cmd==2) || (cmd==4)) { ++ mp->bpp=cmd; ++ minipug_setup(); ++ } ++ break; ++ default : ++ break; ++ } ++#endif ++printk("%s: writ %ld\n",__FUNCTION__,copied); ++ return copied; ++ } ++ // groups of double ints are display buffer update requests ++ else if (size == (size / (sizeof(unsigned int)*2))*(sizeof(unsigned int)*2)) { ++ unsigned int offset; ++ unsigned int count; ++ size_t org_size=size; ++ while (size) { ++ unsigned long copied = copy_from_user(&offset,buf,sizeof(offset)); ++ buf+=sizeof(offset); ++ copied = copy_from_user(&count,buf,sizeof(count)); ++ buf+=sizeof(count); ++ if (offset>=BUFFER_SIZE) ++ printk("%s: ignoring, offset = 0x%x max = 0x%x\n",__FUNCTION__,offset,BUFFER_SIZE-1); ++ else if (offset+count>BUFFER_SIZE) ++ printk("%s: ignoring, offset + count = 0x%x max = 0x%x\n",__FUNCTION__,offset+count,BUFFER_SIZE-1); ++ else { ++// printk("%s: updating count = 0x%x\n",__FUNCTION__,count); ++ update_graphics(mp->buffer+offset,count,offset); ++ } ++ size-=sizeof(unsigned int)*2; ++ } ++ return org_size; ++ } ++ return -EINVAL; ++} ++ ++/* maybe this will be handy in due course */ ++int minipug_ioctl(struct inode *inode, ++ struct file *flip, ++ unsigned int command, ++ unsigned long arg) ++{ ++ int err; ++ err = -EINVAL; ++ return err; ++} ++ ++int minipug_mmap(struct file *filp, struct vm_area_struct *vma) { ++ struct minipug_info *mp= (struct minipug_info *)filp->private_data; ++ ++ if (remap_vmalloc_range(vma, mp->buffer,0)) { ++ printk(KERN_ERR "remap_pfn_range failed in mmtimer.c\n"); ++ return -EAGAIN; ++ } ++ ++ return 0; ++} ++ ++static int proc_read_minipug(struct file * filp, char * buf, ++ size_t nbytes, loff_t *ppos) ++{ ++ char outputbuf[512]; ++ int count=0; ++ // all done in a single read ++ if (*ppos>0) ++ return 0; ++ count += sprintf(&outputbuf[count], "Minipug %d: ready\n Bits per pixel %d\n", ++ minipug[0].display, minipug[0].bpp); ++ count += sprintf(&outputbuf[count], "Minipug %d: ready\n Bits per pixel %d\n", ++ minipug[1].display, minipug[1].bpp); ++ ++ if (count>nbytes) /* Assume output can be read at one time */ ++ return -EINVAL; ++ if (copy_to_user(buf, outputbuf, count)) ++ return -EFAULT; ++ *ppos += count; ++ return count; ++} ++ ++static ssize_t proc_write_minipug(struct file * filp, const char * buffer, ++ size_t count, loff_t *ppos) ++{ ++// struct minipug_info *mp= (struct minipug_info *)filp->private_data; ++ ++// if (strncmp(buff,"reset:",6)==0) ++ ++// newRegValue = simple_strtoul(buffer,&endp,0); ++ /* a bold but simple claim is to have read it all */ ++ return count; ++} ++ ++/* driver initialisation */ ++static int __init minipug_probe ( struct platform_device *pdev) { ++ ++#ifndef CONFIG_BALLOON2_BUILD_TCL_PIKEY2 ++ // if smart media present - cpld cannot be so declare invalid ++ if (balloon_samosa_sm_present()) { ++ printk("%s: samosa bus not present\n",__FUNCTION__); ++ return -ENODEV; ++ } ++#endif ++ ++ if (!minipug_ready(pdev->id)) { ++ printk("%s: minipug %d not ready\n",__FUNCTION__,pdev->id); ++ return -ENODEV; ++ } ++ ++ minipug[pdev->id].buffer=(unsigned char *)vmalloc_user(BUFFER_SIZE); ++ if (!minipug[pdev->id].buffer) { ++ printk("%s: minipug %d not enough memory\n",__FUNCTION__,pdev->id); ++ return -ENOMEM; ++ } ++ ++ active_display=pdev->id; ++ minipug[active_display].bpp=DISPLAY_BPP0; ++ minipug_setup(); ++ ++ printk("Minipug %d display support installed\n",pdev->id); ++ ++ return 0; ++} ++ ++static int __exit minipug_remove (struct platform_device *_dev) ++{ ++ vfree(minipug[_dev->id].buffer); ++ platform_set_drvdata(_dev,NULL); ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int minipug_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ return 0; ++} ++ ++static int minipug_resume(struct platform_device *dev) ++{ ++ active_display=0; ++ minipug_setup(); ++ ++ active_display=1; ++ minipug_setup(); ++ return 0; ++} ++#else ++#define minipug_suspend NULL ++#define minipug_resume NULL ++#endif ++ ++static void minipug_shutdown(struct platform_device *dev) ++{ ++} ++ ++// driver definition ++static struct platform_driver minipug_driver = { ++ .probe = minipug_probe, ++ .shutdown = minipug_shutdown, ++ .remove = __exit_p(minipug_remove), ++ .suspend = minipug_suspend, ++ .resume = minipug_resume, ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "minipug", ++ }, ++}; ++ ++// character device ++static struct cdev minipug_cdev = { ++ .kobj = {.name = "minipug", }, ++ .owner = THIS_MODULE, ++}; ++ ++static dev_t dev; ++#ifdef MINIPUG_CLASS ++static struct class *minipug_class; ++#elif !defined(SAMOSA_CLASS) ++static struct platform_device *minipug_device[2]; ++#endif ++ ++static int __init minipug_init(void) ++{ ++ int ret; ++ ++ // general initialisation ++ spin_lock_init(&minipug_lock); ++ ++ // register a range of device nodes ++ if (major) { ++ dev = MKDEV(major,0); ++ ret = register_chrdev_region(dev, 2, "minipug"); ++ } ++ else { ++ ret = alloc_chrdev_region(&dev, 0, 2, "minipug"); ++ major = MAJOR(dev); ++ } ++ ++ if (ret) ++ goto error; ++ ++ // create a character device handler ++ cdev_init(&minipug_cdev,&minipug_fops); ++ // add character device with 2 entries ++ ret = cdev_add(&minipug_cdev, dev, 2); ++ if (ret) { ++ kobject_put(&minipug_cdev.kobj); ++ goto error_region; ++ } ++ ++#ifdef MINIPUG_CLASS ++ // explicitly create 2 devices via a minipug class ++ // this seems necessary to avoid the problem of platform devices ++ // not sending MAJOR and MINOR fields so udev is unable to ++ // create the device nodes. ++ minipug_class = class_create(THIS_MODULE, "minipug"); ++ if (IS_ERR(minipug_class)) { ++ printk(KERN_ERR "Error creating minipug class.\n"); ++ cdev_del(&minipug_cdev); ++ ret = PTR_ERR(minipug_class); ++ goto error_region; ++ } ++ // create the actual devices ++ device_create(minipug_class, NULL, MKDEV(major, 0), "minipug0"); ++ device_create(minipug_class, NULL, MKDEV(major, 1), "minipug1"); ++#elif defined(SAMOSA_CLASS) ++ // create the actual devices ++ device_create(balloon_samosa_class, NULL, MKDEV(major, 0), "minipug0"); ++ device_create(balloon_samosa_class, NULL, MKDEV(major, 1), "minipug1"); ++#else ++#if 1 ++ minipug_device[0] = platform_device_alloc("minipug", 0); ++ // this is a hack to permit uevents ++ minipug_device[0]->dev.uevent_suppress = 0; ++ minipug_device[1] = platform_device_alloc("minipug", 1); ++ // this is a hack to permit uevents ++ minipug_device[1]->dev.uevent_suppress = 0; ++#else ++ // this seems a way not to have to hack platform_device_alloc ++ // it needs a release function and also doesnt pass MAJOR or MINOR ++ minipug_device[0] = kzalloc(sizeof(struct platform_device), GFP_KERNEL); ++ minipug_device[0]->name = "minipug"; ++ minipug_device[0]->id = 0; ++// minipug_device[0].release = minipug_release; ++ ++ minipug_device[1] = kzalloc(sizeof(struct platform_device), GFP_KERNEL); ++ minipug_device[1]->name = "minipug"; ++ minipug_device[1]->id = 1; ++// minipug_device[1].release = minipug_release; ++#endif ++ ++// both the versions below work fine ++#if 1 ++ platform_device_register(minipug_device[0]); ++ platform_device_register(minipug_device[1]); ++#else ++ platform_add_devices(minipug_device, ARRAY_SIZE(minipug_device)); ++#endif ++#endif ++ ++ // create proc access to displays ++ proc_minipug = create_proc_entry(PROC_MINIPUG,S_IWUSR | S_IRUSR | S_IRGRP | S_IROTH, &proc_root); ++ if (proc_minipug) ++ proc_minipug->proc_fops = &proc_minipug_operations; ++ ++ // register the driver ++ return platform_driver_register(&minipug_driver); ++ ++error_region: ++ unregister_chrdev_region(dev, 2); ++error: ++ return ret; ++} ++ ++static void __exit minipug_exit(void) ++{ ++ // remove proc entry ++ remove_proc_entry(PROC_MINIPUG,&proc_root); ++#ifdef MINIPUG_CLASS ++ // remove devices ++ device_destroy(minipug_class, MKDEV(major, 0)); ++ device_destroy(minipug_class, MKDEV(major, 1)); ++ // remove class ++ class_destroy(minipug_class); ++#elif defined(SAMOSA_CLASS) ++ // remove devices ++ device_destroy(balloon_samosa_class, MKDEV(major, 0)); ++ device_destroy(balloon_samosa_class, MKDEV(major, 1)); ++#else ++ platform_device_unregister(minipug_device[0]); ++ kfree(minipug_device[0]); ++ platform_device_unregister(minipug_device[1]); ++ kfree(minipug_device[1]); ++#endif ++ // remove driver ++ platform_driver_unregister(&minipug_driver); ++ // remove character device ++ cdev_del(&minipug_cdev); ++ // unregister region ++ unregister_chrdev_region(dev, 2); ++} ++ ++module_init(minipug_init); ++module_exit(minipug_exit); ++ ++MODULE_AUTHOR("Nick Bane "); ++MODULE_DESCRIPTION("Minipug display interface via samosa bus on Balloon"); ++MODULE_LICENSE("GPL"); Added: balloon/trunk/kernel/2.6.25.2/balloon3-nand.patch =================================================================== --- balloon/trunk/kernel/2.6.25.2/balloon3-nand.patch (rev 0) +++ balloon/trunk/kernel/2.6.25.2/balloon3-nand.patch 2008-05-11 01:24:31 UTC (rev 479) @@ -0,0 +1,309 @@ +Index: drivers/mtd/nand/Makefile +=================================================================== +--- drivers/mtd/nand/Makefile.orig 2008-05-07 00:21:32.000000000 +0100 ++++ drivers/mtd/nand/Makefile 2008-05-09 15:14:13.000000000 +0100 +@@ -28,6 +28,7 @@ + obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o + obj-$(CONFIG_MTD_NAND_BASLER_EXCITE) += excite_nandflash.o + obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o ++obj-$(CONFIG_MTD_NAND_BALLOON3) += balloon3.o + obj-$(CONFIG_MTD_ALAUDA) += alauda.o + obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o + obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o +Index: drivers/mtd/nand/Kconfig +=================================================================== +--- drivers/mtd/nand/Kconfig.orig 2008-05-07 00:21:32.000000000 +0100 ++++ drivers/mtd/nand/Kconfig 2008-05-09 15:13:36.000000000 +0100 +@@ -290,6 +290,10 @@ + Enables support for NAND Flash interface on PA Semi PWRficient + based boards + ++config MTD_NAND_BALLOON3 ++ tristate "Support for NAND Flash on Balloon3 board" ++ depends on MTD_NAND && MACH_BALLOON3 ++ + config MTD_NAND_NANDSIM + tristate "Support for NAND Flash Simulator" + depends on MTD_PARTITIONS +Index: drivers/mtd/nand/balloon3.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ drivers/mtd/nand/balloon3.c 2008-05-09 15:11:46.000000000 +0100 +@@ -0,0 +1,259 @@ ++/* ++ * Derived from drivers/mtd/nand/sharpsl.c ++ * ++ * by Nick Bane, May 2007 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/* option to ioremap in two small ranges */ ++#define SPLIT_RANGE ++ ++#ifdef SPLIT_RANGE ++/* FIXME - unsure which to use, a word or a block */ ++#define SPLIT_RANGE_SIZE 0x1000 ++//#define SPLIT_RANGE_SIZE 4 ++ ++#define balloon3_phys_ctl_base (BALLOON3_NANDIO_PHYS + BALLOON3_NANDIO_CTL_OFFSET) ++#define balloon3_phys_io_base (BALLOON3_NANDIO_PHYS + BALLOON3_NANDIO_IO_OFFSET) ++static void __iomem *balloon3_io_base = (void __iomem *)(BALLOON3_NANDIO_VIRT + BALLOON3_NANDIO_IO_OFFSET); ++static void __iomem *balloon3_ctl_base = (void __iomem *)(BALLOON3_NANDIO_VIRT + BALLOON3_NANDIO_CTL_OFFSET); ++#define FLASHIO balloon3_io_base /* Flash I/O */ ++#define FLASHCTL balloon3_ctl_base /* Flash Control */ ++#else ++#define balloon3_phys_nand_base (BALLOON3_NANDIO_PHYS) ++static void __iomem *balloon3_nand_base = (void __iomem *)(BALLOON3_NANDIO_VIRT); ++#define FLASHIO (balloon3_nand_base)+BALLOON3_NANDIO_IO_OFFSET /* Flash I/O */ ++#define FLASHCTL (balloon3_nand_base)+BALLOON3_NANDIO_CTL_OFFSET /* Flash Control */ ++#endif ++ ++/* Flash control bits */ ++#define FLWP (1 << 7) ++#define FLCE3 (1 << 5) ++#define FLCE2 (1 << 4) ++#define FLCE1 (1 << 3) ++#define FLCE0 (1 << 2) ++#define FLALE (1 << 1) ++#define FLCLE (1 << 0) ++ ++/* ++ * MTD structure for Balloon3 ++ */ ++static struct mtd_info *balloon3_mtd = NULL; ++ ++/* ++ * Define partitions for flash device ++ */ ++#define DEFAULT_NUM_PARTITIONS 2 ++ ++static int nr_partitions; ++static struct mtd_partition balloon3_nand_default_partition_info[] = { ++ { ++ .name = "Boot", ++ .offset = 0, ++ .size = 4 * 1024 * 1024, ++ }, ++ { ++ .name = "Root fs", ++ .offset = MTDPART_OFS_APPEND , ++ .size = MTDPART_SIZ_FULL , ++ }, ++}; ++ ++static void ++balloon3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) ++{ ++ struct nand_chip *this=mtd->priv; ++ __raw_readsb(this->IO_ADDR_R,buf,len); ++} ++ ++static void ++balloon3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) ++{ ++ struct nand_chip *this=mtd->priv; ++ __raw_writesb(this->IO_ADDR_W,buf,len); ++} ++ ++/* ++ * hardware specific access to control-lines ++ */ ++static unsigned char balloon3_ctl= FLCE0 | FLCE1 | FLCE2 | FLCE3 | FLWP; ++ ++static void ++balloon3_nand_hwcontrol(struct mtd_info* mtd, int cmd, unsigned int ctrl) ++{ ++ struct nand_chip *this = mtd->priv; ++ ++ if (ctrl & NAND_CTRL_CHANGE) { ++ balloon3_ctl &= (FLCE0 | FLCE1 | FLCE2 | FLCE3 | FLWP); ++ balloon3_ctl |= (ctrl & NAND_CLE) ? FLCLE:0; ++ balloon3_ctl |= (ctrl & NAND_ALE) ? FLALE:0; ++ writeb(balloon3_ctl,FLASHCTL); ++ } ++ if (cmd != NAND_CMD_NONE) ++ writeb(cmd,this->IO_ADDR_W); ++} ++ ++#ifdef CONFIG_MTD_PARTITIONS ++const char *part_probes[] = { "cmdlinepart", NULL }; ++#endif ++ ++void ++balloon3_nand_select_chip(struct mtd_info *mtd, int chip) ++{ ++ // deselect all chips ++ balloon3_ctl |= (FLCE0 | FLCE1 | FLCE2 | FLCE3); ++ // do chip select as required ++ switch (chip) { ++ case -1: break; ++ case 0: balloon3_ctl &= ~FLCE0; break; ++ case 1: balloon3_ctl &= ~FLCE1; break; ++ case 2: balloon3_ctl &= ~FLCE2; break; ++ case 3: balloon3_ctl &= ~FLCE3; break; ++ } ++ writeb(balloon3_ctl,FLASHCTL); ++} ++ ++/* ++ * Main initialization routine ++ */ ++int __init ++balloon3_nand_init(void) ++{ ++ struct nand_chip *this; ++ struct mtd_partition* balloon3_partition_info; ++ ++ /* Allocate memory for MTD device structure and private data */ ++ balloon3_mtd = kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), ++ GFP_KERNEL); ++ if (!balloon3_mtd) { ++ printk ("Unable to allocate SharpSL NAND MTD device structure.\n"); ++ return -ENOMEM; ++ } ++ ++ balloon3_mtd->owner = THIS_MODULE; ++ ++#ifdef SPLIT_RANGE ++ /* map physical io adress */ ++ balloon3_io_base = ioremap(balloon3_phys_io_base, SPLIT_RANGE_SIZE); ++ if (!balloon3_io_base) { ++ printk("ioremap to access Balloon3 NAND chip io failed\n"); ++ kfree(balloon3_mtd); ++ return -EIO; ++ } ++ /* map physical ctl adress */ ++ balloon3_ctl_base = ioremap(balloon3_phys_ctl_base, SPLIT_RANGE_SIZE); ++ if (!balloon3_ctl_base) { ++ printk("ioremap to access Balloon3 NAND chip ctl failed\n"); ++ iounmap(balloon3_io_base); ++ kfree(balloon3_mtd); ++ return -EIO; ++ } ++#else ++ balloon3_nand_base = ioremap(balloon3_phys_nand_base, NANDIO_LENGTH); ++ if(!balloon3_nand_base){ ++ printk("ioremap to access Balloon3 NAND chip io failed\n"); ++ kfree(balloon3_mtd); ++ return -EIO; ++ } ++#endif ++ ++ /* Get pointer to private data */ ++ this = (struct nand_chip *) (&balloon3_mtd[1]); ++ ++ /* Initialize structures */ ++ memset((char *) balloon3_mtd, 0, sizeof(struct mtd_info)); ++ memset((char *) this, 0, sizeof(struct nand_chip)); ++ ++ /* Link the private data with the MTD structure */ ++ balloon3_mtd->priv = this; ++ ++ /* initialise lines */ ++ writeb(balloon3_ctl,FLASHCTL); ++ ++ /* initialise mtd nand i/o */ ++ this->IO_ADDR_R = FLASHIO; ++ this->IO_ADDR_W = FLASHIO; ++ this->read_buf=balloon3_nand_read_buf; ++ this->write_buf=balloon3_nand_write_buf; ++ this->cmd_ctrl = balloon3_nand_hwcontrol; ++// this->dev_ready = balloon3_nand_dev_ready; ++ this->select_chip=balloon3_nand_select_chip; ++ ++ /* 20 us command delay time */ ++/* empirical increase needed for 2K nand it seems */ ++ this->chip_delay = 50; ++ this->ecc.mode = NAND_ECC_SOFT; ++ ++ /* Scan to find existence of the device */ ++ if (nand_scan(balloon3_mtd,4)) ++ { ++#ifdef SPLIT_RANGE ++ iounmap(balloon3_io_base); ++ iounmap(balloon3_ctl_base); ++#else ++ iounmap(balloon3_nand_base); ++#endif ++ kfree(balloon3_mtd); ++ return -ENXIO; ++ } ++ ++ /* Register the partitions */ ++ balloon3_mtd->name = "balloon3-nand"; ++ ++#ifdef CONFIG_MTD_PARTITIONS ++ nr_partitions = parse_mtd_partitions(balloon3_mtd, part_probes, ++ &balloon3_partition_info, 0); ++#else ++ nr_partitions=0; ++#endif ++ if (nr_partitions <= 0) { ++ nr_partitions = DEFAULT_NUM_PARTITIONS; ++ balloon3_partition_info = balloon3_nand_default_partition_info; ++ } ++ ++ add_mtd_partitions(balloon3_mtd, balloon3_partition_info, nr_partitions); ++ ++ /* Return happy */ ++ return 0; ++} ++module_init(balloon3_nand_init); ++ ++/* ++ * Clean up routine ++ */ ++static void __exit balloon3_nand_cleanup(void) ++{ ++ /* Release resources, unregister device */ ++ nand_release(balloon3_mtd); ++ ++#ifdef SPLIT_RANGE ++ iounmap(balloon3_io_base); ++ iounmap(balloon3_ctl_base); ++#else ++ iounmap(balloon3_nand_base); ++#endif ++ ++ /* Free the MTD device structure */ ++ kfree(balloon3_mtd); ++} ++module_exit(balloon3_nand_cleanup); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Nick Bane "); ++MODULE_DESCRIPTION("Device specific logic for NAND flash on Balloon3 board"); +Index: include/asm-arm/arch-pxa/balloon3.h +=================================================================== +--- include/asm-arm/arch-pxa/balloon3.h.orig 2008-05-09 15:09:59.000000000 +0100 ++++ include/asm-arm/arch-pxa/balloon3.h 2008-05-09 15:11:46.000000000 +0100 +@@ -51,6 +51,13 @@ + /* backlight control */ + #define BALLOON3_GPIO_RUN_BACKLIGHT (99) + ++/* add this for balloon3 nand-driver - FIXME driver needs to use above style*/ ++#define BALLOON3_NANDIO_PHYS BALLOON3_FPGA_PHYS ++#define BALLOON3_NANDIO_VIRT BALLOON3_FPGA_VIRT ++#define BALLOON3_NANDIO_IO_OFFSET 0x00e00000 ++#define BALLOON3_NANDIO_CTL2_OFFSET 0x00e00010 ++#define BALLOON3_NANDIO_CTL_OFFSET 0x00e00014 ++ + + #define BALLOON3_GPIO_S0_CD (105) + #define BALLOON3_GPIO_S1_CD (105) // FIXME clearly needs changing for real world Added: balloon/trunk/kernel/2.6.25.2/balloon3-pcmcia.patch =================================================================== --- balloon/trunk/kernel/2.6.25.2/balloon3-pcmcia.patch (rev 0) +++ balloon/trunk/kernel/2.6.25.2/balloon3-pcmcia.patch 2008-05-11 01:24:31 UTC (rev 479) @@ -0,0 +1,240 @@ +Index: drivers/pcmcia/pxa2xx_balloon3.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ drivers/pcmcia/pxa2xx_balloon3.c 2008-05-09 15:11:27.000000000 +0100 +@@ -0,0 +1,223 @@ ++/* ++ * linux/drivers/pcmcia/pxa2xx_balloon3.c ++ * ++ * Mainstone PCMCIA specific routines. ++ * ++ * Created: May 12, 2004 ++ * Author: Nicolas Pitre ++ * Copyright: MontaVista Software Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * Modified for Balloon3 board by N C Bane May 2006 ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include "soc_common.h" ++ ++//#define TWO_SOCKETS ++//#define FAKE_STATUS ++ ++// these are a list of interrupt sources that provokes a polled check of status ++static struct pcmcia_irqs irqs[] = { ++ { 0, BALLOON3_S0_CD_IRQ, "PCMCIA0 CD" }, ++#ifdef TWO_SOCKETS ++// { 1, BALLOON3_S1_CD_IRQ, "PCMCIA1 CD" }, ++#endif ++ { 0, BALLOON3_BP_NSTSCHG_IRQ, "PCMCIA0 STSCHG" }, ++#ifdef TWO_SOCKETS ++// { 1, BALLOON3_BP_NSTSCHG_IRQ, "PCMCIA1 STSCHG" }, ++#endif ++}; ++ ++static int balloon3_pcmcia_hw_init(struct soc_pcmcia_socket *skt) ++{ ++ /* ++ * Setup default state of GPIO outputs ++ * before we enable them as outputs. ++ */ ++ GPSR(GPIO48_nPOE) = ++ GPIO_bit(GPIO48_nPOE) | ++ GPIO_bit(GPIO49_nPWE) | ++ GPIO_bit(GPIO50_nPIOR) | ++ GPIO_bit(GPIO51_nPIOW) | ++ GPIO_bit(GPIO85_nPCE_1) | ++ GPIO_bit(GPIO54_nPCE_2); ++ ++ pxa_gpio_mode(GPIO48_nPOE_MD); ++ pxa_gpio_mode(GPIO49_nPWE_MD); ++ pxa_gpio_mode(GPIO50_nPIOR_MD); ++ pxa_gpio_mode(GPIO51_nPIOW_MD); ++ pxa_gpio_mode(GPIO85_nPCE_1_MD); ++ pxa_gpio_mode(GPIO54_nPCE_2_MD); ++ pxa_gpio_mode(GPIO79_pSKTSEL_MD); ++ pxa_gpio_mode(GPIO55_nPREG_MD); ++ pxa_gpio_mode(GPIO56_nPWAIT_MD); ++ pxa_gpio_mode(GPIO57_nIOIS16_MD); ++ ++#ifdef TWO_SOCKETS ++// skt->irq = (skt->nr == 0) ? BALLOON3_S0_IRQ : BALLOON3_S1_IRQ; ++#else ++ skt->irq = BALLOON3_BP_CF_NRDY_IRQ; ++ ++#endif ++ printk("%s: socket irq is %d, requesting status change irqs\n",__FUNCTION__,skt->irq); ++ ++ return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs)); ++} ++ ++static void balloon3_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) ++{ ++ soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs)); ++} ++ ++static unsigned long balloon3_pcmcia_status[2]; ++ ++static void balloon3_pcmcia_socket_state(struct soc_pcmcia_socket *skt, ++ struct pcmcia_state *state) ++{ ++#ifdef FAKE_STATUS ++ state->detect = 0; ++ state->ready = 1; ++ state->bvd1 = 0; ++ state->bvd2 = 0; ++ state->vs_3v = 1; ++ state->vs_Xv = 0; ++ state->wrprot = 0; /* not available */ ++#else ++ unsigned long status, flip; ++ ++#ifdef TWO_SOCKETS ++// status = (skt->nr == 0) ? BALLOON3_PCMCIA0_REG : BALLOON3_PCMCIA1_REG; ++#else ++ status = BALLOON3_PCMCIA0_REG; ++#endif ++ flip = (status ^ balloon3_pcmcia_status[skt->nr]) & BALLOON3_PCMCIA_nSTSCHG_BVD1; ++ ++ /* ++ * Workaround for STSCHG which can't be deasserted: ++ * We therefore disable/enable corresponding IRQs ++ * as needed to avoid IRQ locks. ++ */ ++ if (flip) { ++ balloon3_pcmcia_status[skt->nr] = status; ++ if (status & BALLOON3_PCMCIA_nSTSCHG_BVD1) ++#ifdef TWO_SOCKETS ++// enable_irq( (skt->nr == 0) ? BALLOON3_S0_STSCHG_IRQ ++// : BALLOON3_S1_STSCHG_IRQ ); ++#else ++ enable_irq(BALLOON3_BP_NSTSCHG_IRQ); ++#endif ++ else ++#ifdef TWO_SOCKETS ++// disable_irq( (skt->nr == 0) ? BALLOON3_S0_STSCHG_IRQ ++// : BALLOON3_S1_STSCHG_IRQ ); ++#else ++ disable_irq(BALLOON3_BP_NSTSCHG_IRQ); ++#endif ++ } ++ ++#ifdef TWO_SOCKETS ++ state->detect = (skt->nr == 0) ? ((GPLR(BALLOON3_GPIO_S0_CD) & GPIO_bit(BALLOON3_GPIO_S0_CD)) ? 0 : 1):0; ++#else ++ state->detect = (GPLR(BALLOON3_GPIO_S0_CD) & GPIO_bit(BALLOON3_GPIO_S0_CD)) ? 0 : 1; ++#endif ++ state->ready = (status & BALLOON3_PCMCIA_nIRQ) ? 1 : 0; ++ state->bvd1 = (status & BALLOON3_PCMCIA_nSTSCHG_BVD1) ? 1 : 0; ++ state->bvd2 = 0; //not available ++ state->vs_3v = 1; //Always true its a CF card ++ state->vs_Xv = 0; //not available ++ state->wrprot = 0; /* not available */ ++#endif ++} ++ ++static int balloon3_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, ++ const socket_state_t *state) ++{ ++ unsigned long power = 0; ++ int ret = 0; ++ ++ if (state->flags & SS_RESET) ++ power |= BALLOON3_PCMCIA_RESET; ++ ++ switch (skt->nr) { ++ case 0: BALLOON3_PCMCIA0_REG = power; break; ++#ifdef TWO_SOCKETS ++ case 1: BALLOON3_PCMCIA1_REG = power; break; ++#endif ++ default: ret = -1; ++ } ++ ++ return ret; ++} ++ ++static void balloon3_pcmcia_socket_init(struct soc_pcmcia_socket *skt) ++{ ++ printk("%s: socket %d initialised\n",__FUNCTION__, skt->nr); ++} ++ ++static void balloon3_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) ++{ ++} ++ ++static struct pcmcia_low_level balloon3_pcmcia_ops = { ++ .owner = THIS_MODULE, ++ .hw_init = balloon3_pcmcia_hw_init, ++ .hw_shutdown = balloon3_pcmcia_hw_shutdown, ++ .socket_state = balloon3_pcmcia_socket_state, ++ .configure_socket = balloon3_pcmcia_configure_socket, ++ .socket_init = balloon3_pcmcia_socket_init, ++ .socket_suspend = balloon3_pcmcia_socket_suspend, ++#ifdef TWO_SOCKETS ++ .nr = 2, ++#else ++ .nr = 1, ++#endif ++}; ++ ++static struct platform_device *balloon3_pcmcia_device; ++ ++static int __init balloon3_pcmcia_init(void) ++{ ++ int ret; ++ ++ balloon3_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); ++ if (!balloon3_pcmcia_device) ++ return -ENOMEM; ++ ++ balloon3_pcmcia_device->dev.platform_data = &balloon3_pcmcia_ops; ++ ++ ret = platform_device_add(balloon3_pcmcia_device); ++ ++ if (ret) ++ platform_device_put(balloon3_pcmcia_device); ++ ++ return ret; ++} ++ ++static void __exit balloon3_pcmcia_exit(void) ++{ ++ platform_device_unregister(balloon3_pcmcia_device); ++} ++ ++fs_initcall(balloon3_pcmcia_init); ++module_exit(balloon3_pcmcia_exit); ++ ++MODULE_LICENSE("GPL"); +Index: drivers/pcmcia/Makefile +=================================================================== +--- drivers/pcmcia/Makefile.orig 2008-05-07 00:21:32.000000000 +0100 ++++ drivers/pcmcia/Makefile 2008-05-09 15:11:27.000000000 +0100 +@@ -69,6 +69,7 @@ + + pxa2xx_cs-$(CONFIG_ARCH_LUBBOCK) += pxa2xx_lubbock.o sa1111_generic.o + pxa2xx_cs-$(CONFIG_MACH_MAINSTONE) += pxa2xx_mainstone.o ++pxa2xx_cs-$(CONFIG_MACH_BALLOON3) += pxa2xx_balloon3.o + pxa2xx_cs-$(CONFIG_PXA_SHARPSL) += pxa2xx_sharpsl.o + pxa2xx_cs-$(CONFIG_MACH_ARMCORE) += pxa2xx_cm_x270.o + Added: balloon/trunk/kernel/2.6.25.2/balloon3-samosa.patch =================================================================== --- balloon/trunk/kernel/2.6.25.2/balloon3-samosa.patch (rev 0) +++ balloon/trunk/kernel/2.6.25.2/balloon3-samosa.patch 2008-05-11 01:24:31 UTC (rev 479) @@ -0,0 +1,356 @@ +Index: linux-2.6.25.2/drivers/char/samosa.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-2.6.25.2/drivers/char/samosa.h 2008-05-09 15:10:03.000000000 +0100 +@@ -0,0 +1,25 @@ ++/* ++ * include/asm-arm/arch-sa1100/balloon2_samosa.h ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _SAMOSA_H_ ++#define _SAMOSA_H_ ++ ++#include "linux/device.h" ++ ++extern struct class *balloon_samosa_class; ++ ++/* samosa bus usage functions */ ++int balloon_samosa_read8(unsigned char reg); ++void balloon_samosa_write8(unsigned char reg, unsigned char value); ++//int balloon_samosa_read16(unsigned char reg); ++//int balloon_samosa_write16(unsigned char reg, unsigned char value); ++void balloon_samosa_write_block8(unsigned char reg, const unsigned char *value, unsigned int count); ++void balloon_samosa_write_repeat8(unsigned char reg, unsigned char value, unsigned int count); ++int balloon_samosa_sm_present(void); ++ ++#endif +Index: linux-2.6.25.2/drivers/char/Makefile +=================================================================== +--- linux-2.6.25.2.orig/drivers/char/Makefile 2008-05-07 00:21:32.000000000 +0100 ++++ linux-2.6.25.2/drivers/char/Makefile 2008-05-09 15:10:03.000000000 +0100 +@@ -112,6 +112,8 @@ + obj-$(CONFIG_JS_RTC) += js-rtc.o + js-rtc-y = rtc.o + ++obj-$(CONFIG_SAMOSA) += samosa.o ++ + # Files generated that shall be removed upon make clean + clean-files := consolemap_deftbl.c defkeymap.c + +Index: linux-2.6.25.2/drivers/char/Kconfig +=================================================================== +--- linux-2.6.25.2.orig/drivers/char/Kconfig 2008-05-07 00:21:32.000000000 +0100 ++++ linux-2.6.25.2/drivers/char/Kconfig 2008-05-09 15:10:03.000000000 +0100 +@@ -1049,5 +1049,15 @@ + + source "drivers/s390/char/Kconfig" + ++config SAMOSA ++ tristate "Balloon samosa bus" ++ depends on MACH_BALLOON3 || MACH_BALLOON2 ++ default y ++ help ++ Simple IO bus (via FPGA/CPLD) on Balloonboard. 8 bit on ++ Balloon2, 8 or 16 bit on Balloon3. You normally want this ++ unless you are using the bus lines for something else. ++ ++ + endmenu + +Index: linux-2.6.25.2/drivers/char/samosa.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-2.6.25.2/drivers/char/samosa.c 2008-05-09 15:10:03.000000000 +0100 +@@ -0,0 +1,288 @@ ++/* ++ * linux/arch/arm/mach-sa1100/balloon3_samosa.c ++ * Copyright (c) N C Bane nick@cecomputing.co.uk ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++#include ++ ++#include ++ ++#include "samosa.h" ++ ++#ifdef CONFIG_MACH_BALLOON3 ++/* balloon3 version */ ++ ++/* Samosa bus on Balloon3 is dead simple. Address latching and read/write enable ++ * are taken care of automaticaly by FPGA/CPLD logic. So just write address to address regsiter ++ * then read or write data from/to data regsiter ++ */ ++ ++int balloon_samosa_read8(unsigned char reg) ++{ ++ int ret; ++ printk(KERN_DEBUG "Samosa byte read:reg %x, ",reg); ++ BALLOON3_SAMOSA_ADDR_REG = reg; ++ ret = BALLOON3_SAMOSA_DATA_REG; ++ printk(KERN_DEBUG "returned:%x\n",ret); ++ return ret; ++} ++ ++void balloon_samosa_write8(unsigned char reg, unsigned char value) ++{ ++ printk(KERN_DEBUG "Samosa byte write:value:%x to reg %x\n",value, reg); ++ BALLOON3_SAMOSA_ADDR_REG = reg; ++ BALLOON3_SAMOSA_DATA_REG = value; ++} ++ ++void balloon_samosa_write_block8(unsigned char reg, const unsigned char *value, unsigned int count) ++{ ++ printk(KERN_DEBUG "Samosa block byte write:count %d\n",count); /*print out data? */ ++ BALLOON3_SAMOSA_ADDR_REG = reg; ++ while (count--) BALLOON3_SAMOSA_DATA_REG=*(value)++; ++} ++ ++void balloon_samosa_write_repeat8(unsigned char reg, unsigned char value, unsigned int count) ++{ ++ printk(KERN_DEBUG "Samosa repeat byte write:value:%x, count %d\n",value, count); ++ BALLOON3_SAMOSA_ADDR_REG = reg; ++ while (count--) BALLOON3_SAMOSA_DATA_REG=value; ++} ++ ++/* fixme - this should probably do something...*/ ++int balloon_samosa_sm_present(void) ++{ ++ return 0; ++} ++ ++#endif ++ ++#ifdef CONFIG_MACH_BALLOON2 ++ ++/* ++ * samosa bus support - Balloon2 ++ * On Balloon2 the samosa bus is a generalised extension of the nand bus using the ++ * original SmartMedia socket address ++ */ ++#include ++ ++#define SAMOSA_CLE_BIT 0 ++#define SAMOSA_ALE_BIT 1 ++#define SAMOSA_NCE0_BIT 2 ++#define SAMOSA_NCE1_BIT 3 ++#define SAMOSA_NCE2_BIT 4 ++#define SAMOSA_NCE3_BIT 5 ++#define SAMOSA_NSE_BIT 6 ++#define SAMOSA_NWP_BIT 7 ++#define SAMOSA_SIXTEEN_BIT SAMOSA_CLE_BIT ++#define SAMOSA_PLAIT_BUS_BIT 0 ++ ++/* samosa bus access */ ++unsigned int balloon_samosa_get_data_address(void); ++int balloon_samosa_device_selected(unsigned int d); ++int balloon_samosa_device_select(int d, int plait_bus); ++void balloon_samosa_set_ctrl(u8 mask, u8 value); ++int balloon_samosa_sm_present(void); ++int balloon_samosa_nand_ready(void *device); ++ ++ ++#define BALLOON_SAMOSA_IO_ADDR 0xf3000000 /* Common NAND data port */ ++#define BALLOON_SAMOSA_CTRL_ADDR 0xf3800000 /* Common NAND ALE CLE and NCEx write-only port */ ++#define BALLOON_SAMOSA_CTRL2_ADDR 0xf3600000 /* Second control register */ ++ ++#define BALLOON_SAMOSA_CE_MASK ((1 << SAMOSA_NCE0_BIT) | \ ++ (1 << SAMOSA_NCE1_BIT) | (1 << SAMOSA_NCE2_BIT) | \ ++ (1 << SAMOSA_NCE3_BIT)) ++ ++/* standby values */ ++static u8 balloon_samosa_ctrl_image = (1 << SAMOSA_NWP_BIT) | ++ (1 << SAMOSA_NCE0_BIT) | (1 << SAMOSA_NCE1_BIT) | ++ (1 << SAMOSA_NCE2_BIT) | (1 << SAMOSA_NCE3_BIT); ++static u8 balloon_samosa_ctrl2_image = 0; ++ ++unsigned int balloon_samosa_get_data_address(void) ++{ ++ return BALLOON_SAMOSA_IO_ADDR; ++} ++EXPORT_SYMBOL(balloon_samosa_get_data_address); ++ ++static int balloon_samosa_plait_bus(void) ++{ ++ if (balloon_has(BALLOON_SAMOSA_PLAIT_SYS)) { ++ balloon_samosa_ctrl2_image |= (1 << SAMOSA_PLAIT_BUS_BIT); ++ writeb(balloon_samosa_ctrl2_image, BALLOON_SAMOSA_CTRL2_ADDR); ++ } ++ return 0; ++} ++ ++static int balloon_samosa_unplait_bus(void) ++{ ++ if (balloon_has(BALLOON_SAMOSA_PLAIT_SYS)) { ++ balloon_samosa_ctrl2_image &= ~(1 << SAMOSA_PLAIT_BUS_BIT); ++ writeb(balloon_samosa_ctrl2_image, BALLOON_SAMOSA_CTRL2_ADDR); ++ } ++ return 0; ++} ++ ++int balloon_samosa_device_selected(unsigned int d) ++{ ++ switch (d) { ++ case 0: ++ return (balloon_samosa_ctrl_image & ++ (1 << SAMOSA_NCE0_BIT)) ? 0:1; ++ case 1: ++ return (balloon_samosa_ctrl_image & ++ (1 << SAMOSA_NCE1_BIT)) ? 0:1; ++ case 2: ++ return (balloon_samosa_ctrl_image & ++ (1 << SAMOSA_NCE2_BIT)) ? 0:1; ++ case 3: ++ return (balloon_samosa_ctrl_image & ++ (1 << SAMOSA_NCE3_BIT)) ? 0:1; ++ default: ++ return 0; ++ } ++} ++EXPORT_SYMBOL(balloon_samosa_device_selected); ++ ++int balloon_samosa_device_select(int d, int plait_bus) ++{ ++ if (balloon_samosa_device_selected(d)) ++ return 0; ++ ++ switch (d) { ++ case -1: ++ /* Deselect everything */ ++ balloon_samosa_ctrl_image |= BALLOON_SAMOSA_CE_MASK; ++ break; ++ case 0: ++ if ((balloon_samosa_ctrl_image & BALLOON_SAMOSA_CE_MASK) != ++ BALLOON_SAMOSA_CE_MASK) { ++ printk(KERN_WARNING "balloon_samosa_device_select: Trying to select chip %d but balloon_samosa_ctrl_image is 0x%x\n", d, balloon_samosa_ctrl_image); ++ } ++ balloon_samosa_ctrl_image |= BALLOON_SAMOSA_CE_MASK; ++ balloon_samosa_ctrl_image &= ~(1 << SAMOSA_NCE0_BIT); ++ break; ++ case 1: ++ if ((balloon_samosa_ctrl_image & BALLOON_SAMOSA_CE_MASK) != ++ BALLOON_SAMOSA_CE_MASK) { ++ printk(KERN_WARNING "balloon_samosa_device_select: Trying to select chip %d but balloon_samosa_ctrl_image is 0x%x\n", d, balloon_samosa_ctrl_image); ++ } ++ balloon_samosa_ctrl_image |= BALLOON_SAMOSA_CE_MASK; ++ balloon_samosa_ctrl_image &= ~(1 << SAMOSA_NCE1_BIT); ++ break; ++ case 2: ++ if ((balloon_samosa_ctrl_image & BALLOON_SAMOSA_CE_MASK) != ++ BALLOON_SAMOSA_CE_MASK) { ++ printk(KERN_WARNING "balloon_samosa_device_select: Trying to select chip %d but balloon_samosa_ctrl_image is 0x%x\n", d, balloon_samosa_ctrl_image); ++ } ++ balloon_samosa_ctrl_image |= BALLOON_SAMOSA_CE_MASK; ++ balloon_samosa_ctrl_image &= ~(1 << SAMOSA_NCE2_BIT); ++ break; ++ case 3: ++ if ((balloon_samosa_ctrl_image & BALLOON_SAMOSA_CE_MASK) != ++ BALLOON_SAMOSA_CE_MASK) { ++ printk(KERN_WARNING "balloon_samosa_device_select: Trying to select chip %d but balloon_samosa_ctrl_image is 0x%x\n", d, balloon_samosa_ctrl_image); ++ } ++ balloon_samosa_ctrl_image |= BALLOON_SAMOSA_CE_MASK; ++ balloon_samosa_ctrl_image &= ~(1 << SAMOSA_NCE3_BIT); ++ break; ++ default: ++ BUG(); ++ } ++ writeb(balloon_samosa_ctrl_image, BALLOON_SAMOSA_CTRL_ADDR); ++ ++ /* default is plaited for 8-bit nand access */ ++ if (plait_bus) ++ balloon_samosa_plait_bus(); ++ else ++ balloon_samosa_unplait_bus(); ++ ++ return 0; ++} ++EXPORT_SYMBOL(balloon_samosa_device_select); ++ ++void balloon_samosa_set_ctrl(u8 mask, u8 value) ++{ ++ balloon_samosa_ctrl_image &= ~mask; ++ balloon_samosa_ctrl_image |= value; ++ ++ writeb(balloon_samosa_ctrl_image, BALLOON_SAMOSA_CTRL_ADDR); ++} ++EXPORT_SYMBOL(balloon_samosa_set_ctrl); ++ ++int balloon_samosa_nand_ready(void *mtd_device) ++{ ++ return GPLR & BALLOON_GPIO205_NAND_RNB; ++} ++EXPORT_SYMBOL(balloon_samosa_nand_ready); ++ ++#endif /* end of balloon2 version */ ++ ++// generic char device add/destroy ++//extern struct bus_type samosa_bus_type; ++struct class *balloon_samosa_class; ++EXPORT_SYMBOL(balloon_samosa_class); ++ ++#if 0 ++static dev_t dev; ++static int major; ++static int minor; ++ ++dev_t balloon_samosa_device_create(const char *name) { ++} ++EXPORT_SYMBOL(balloon_samosa_device_create); ++ ++dev_t balloon_samosa_device_destroy(dev_t dev) { ++} ++EXPORT_SYMBOL(balloon_samosa_device_destroy); ++#endif ++ ++static int __init init_samosa(void) ++{ ++ unsigned int ver; ++ printk(KERN_INFO "Samosa services initialised.\n"); ++ //!!debug: test CPLD reading ++ ver = BALLOON3_VERSION_REG; ++ printk(KERN_DEBUG "VHDL logic version (memread):%08X\n", ver); ++ //ver = (*(void __iomem *)(BALLOON3_FPGA_VIRT+0x00e0001c)); ++ //printk(KERN_DEBUG "VHDL logic version (IOread) :%x\n", ver); ++ balloon_samosa_class = class_create(THIS_MODULE, "samosa"); ++ return 0; ++} ++ ++static void __exit cleanup_samosa(void) ++{ ++ class_destroy(balloon_samosa_class); ++} ++ ++module_init(init_samosa); ++module_exit(cleanup_samosa); ++ ++EXPORT_SYMBOL(balloon_samosa_read8); ++EXPORT_SYMBOL(balloon_samosa_write8); ++EXPORT_SYMBOL(balloon_samosa_write_block8); ++EXPORT_SYMBOL(balloon_samosa_write_repeat8); ++EXPORT_SYMBOL(balloon_samosa_sm_present); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Nick Bane "); ++MODULE_DESCRIPTION("samosa bus interface\n"); Added: balloon/trunk/kernel/2.6.25.2/balloon3-vga.patch =================================================================== --- balloon/trunk/kernel/2.6.25.2/balloon3-vga.patch (rev 0) +++ balloon/trunk/kernel/2.6.25.2/balloon3-vga.patch 2008-05-11 01:24:31 UTC (rev 479) @@ -0,0 +1,319 @@ +Index: linux-2.6.25.2/arch/arm/mach-pxa/Kconfig +=================================================================== +--- linux-2.6.25.2.orig/arch/arm/mach-pxa/Kconfig 2008-05-09 18:31:24.000000000 +0100 ++++ linux-2.6.25.2/arch/arm/mach-pxa/Kconfig 2008-05-09 18:31:24.000000000 +0100 +@@ -149,11 +149,35 @@ + endchoice + + if MACH_BALLOON3 ++ ++choice ++ prompt "Balloon 3 LCD configuration" ++ + config BALLOON3_TOPPOLY + bool "Toppoly LCD panel on Balloon3" + help + Say Y to add support for the Toppoly + QVGA/VGA LCD display on a Balloon3 board ++ ++config BALLOON3_VGA ++ bool "VGA (640x480 62Hz) monitor output" ++ help ++ Say Y to add support for VGA output ++ on a Balloon3 board ++ ++config BALLOON3_SVGA ++ bool "SVGA (800x600 52Hz) monitor output" ++ help ++ Say Y to add support for SVGA output ++ on a Balloon3 board ++ ++config BALLOON3_NODISPLAY ++ bool "No LCD output" ++ help ++ Say Y for no LCD output on Balloon3 ++ ++endchoice ++ + endif + + if PXA_SHARPSL +Index: linux-2.6.25.2/arch/arm/mach-pxa/balloon3.c +=================================================================== +--- linux-2.6.25.2.orig/arch/arm/mach-pxa/balloon3.c 2008-05-09 18:31:24.000000000 +0100 ++++ linux-2.6.25.2/arch/arm/mach-pxa/balloon3.c 2008-05-09 18:31:24.000000000 +0100 +@@ -217,8 +217,20 @@ + #endif + } + ++// note here that only certain values of pixclock make sense, because the pixel clock ++// is derived by dividing LCLK (104MHz) by an integer even though it's specified down ++// to the picosecond. ++// The divisor integer must be even if LCCR4_PCCDIV is not set, but can be odd if ++// LCCR4_PCDDIV is set. ++// Divisor pixclock Pixel clock frequency ++// 6 57600 17.333MHz ++// 5 48000 20.8MHz *requires LCCR4_PCDDIV set* ++// 4 38400 26MHz ++// 3 28800 34.667MHz *requires LCCR4_PCDDIV set* ++// 2 19200 52MHz *generally too high to be useful, leaves no DMA bandwidth for anything else * ++ + #ifdef CONFIG_BALLOON3_TOPPOLY +-static struct pxafb_mode_info toppoly_mode __initdata = { ++static struct pxafb_mode_info balloon3_lcd_mode __initdata = { + .pixclock = 38000, + .xres = 480, + .yres = 640, +@@ -236,6 +248,57 @@ + .num_modes = 1, + .lccr0 = LCCR0_Act, + .lccr3 = LCCR3_PCP, ++ .lccr4 = 0, ++ .pxafb_backlight_power = balloon3_backlight_power, ++}; ++ ++#endif ++ ++#ifdef CONFIG_BALLOON3_VGA ++static struct pxafb_mode_info balloon3_lcd_mode __initdata = { ++ .pixclock = 38400, ++ .xres = 640, ++ .yres = 480, ++ .bpp = 16, ++ .hsync_len = 64, ++ .left_margin = 88, ++ .right_margin = 32, ++ .vsync_len = 2, ++ .upper_margin = 32, ++ .lower_margin = 11, ++ .sync = 0, ++}; ++ ++static struct pxafb_mach_info balloon3_pxafb_info = { ++ .num_modes = 1, ++ .lccr0 = LCCR0_Act, ++ .lccr3 = LCCR3_PCP, ++ .lccr4 = 0, ++ .pxafb_backlight_power = balloon3_backlight_power, ++}; ++ ++#endif ++ ++#ifdef CONFIG_BALLOON3_SVGA ++static struct pxafb_mode_info balloon3_lcd_mode __initdata = { ++ .pixclock = 28800, ++ .xres = 800, ++ .yres = 600, ++ .bpp = 16, ++ .hsync_len = 64, ++ .left_margin = 152, ++ .right_margin = 40, ++ .vsync_len = 4, ++ .upper_margin = 23, ++ .lower_margin = 1, ++ .sync = 0, ++}; ++ ++static struct pxafb_mach_info balloon3_pxafb_info = { ++ .num_modes = 1, ++ .lccr0 = LCCR0_Act, ++ .lccr3 = LCCR3_PCP, ++ .lccr4 = LCCR4_PCDDIV, + .pxafb_backlight_power = balloon3_backlight_power, + }; + +@@ -399,8 +462,8 @@ + + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + +-#ifdef CONFIG_BALLOON3_TOPPOLY +- balloon3_pxafb_info.modes = &toppoly_mode; ++#ifndef CONFIG_BALLOON3_NODISPLAY ++ balloon3_pxafb_info.modes = &balloon3_lcd_mode; + set_pxa_fb_info(&balloon3_pxafb_info); + #endif + +Index: linux-2.6.25.2/drivers/video/pxafb.c +=================================================================== +--- linux-2.6.25.2.orig/drivers/video/pxafb.c 2008-05-09 18:31:24.000000000 +0100 ++++ linux-2.6.25.2/drivers/video/pxafb.c 2008-05-09 18:36:24.000000000 +0100 +@@ -537,9 +537,12 @@ + * speeds */ + pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000); + pcd *= pixclock; +- do_div(pcd, 100000000 * 2); +- /* no need for this, since we should subtract 1 anyway. they cancel */ +- /* pcd += 1; */ /* make up for integer math truncations */ ++ /* also take into account LCCR4 PCDDIV bit */ ++ if(LCCR4 & LCCR4_PCDDIV) { ++ do_div(pcd, 100000000); ++ } else { ++ do_div(pcd, 100000000 * 2); ++ } + return (unsigned int)pcd; + } + +@@ -667,10 +670,13 @@ + if (pcd) + new_regs.lccr3 |= LCCR3_PixClkDiv(pcd); + ++ new_regs.lccr4 = fbi->lccr4; ++ + pr_debug("nlccr0 = 0x%08x\n", new_regs.lccr0); + pr_debug("nlccr1 = 0x%08x\n", new_regs.lccr1); + pr_debug("nlccr2 = 0x%08x\n", new_regs.lccr2); + pr_debug("nlccr3 = 0x%08x\n", new_regs.lccr3); ++ pr_debug("nlccr4 = 0x%08x\n", new_regs.lccr4); + + /* Update shadow copy atomically */ + local_irq_save(flags); +@@ -745,8 +751,7 @@ + fbi->reg_lccr1 = new_regs.lccr1; + fbi->reg_lccr2 = new_regs.lccr2; + fbi->reg_lccr3 = new_regs.lccr3; +- fbi->reg_lccr4 = LCCR4 & (~LCCR4_PAL_FOR_MASK); +- fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK); ++ fbi->reg_lccr4 = new_regs.lccr4; + set_hsync_time(fbi, pcd); + local_irq_restore(flags); + +@@ -756,6 +761,7 @@ + */ + if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) || + (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) || ++ (LCCR4 != fbi->reg_lccr4) || + (FDADR0 != fbi->fdadr0) || (FDADR1 != fbi->fdadr1)) + pxafb_schedule_work(fbi, C_REENABLE); + +@@ -833,11 +839,13 @@ + pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1); + pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2); + pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3); ++ pr_debug("reg_lccr4 0x%08x\n", (unsigned int) fbi->reg_lccr4); + + /* enable LCD controller clock */ + clk_enable(fbi->clk); + + /* Sequence from 11.7.10 */ ++ LCCR4 = fbi->reg_lccr4; + LCCR3 = fbi->reg_lccr3; + LCCR2 = fbi->reg_lccr2; + LCCR1 = fbi->reg_lccr1; +@@ -1029,7 +1037,8 @@ + case CPUFREQ_POSTCHANGE: + pcd = get_pcd(fbi, fbi->fb.var.pixclock); + set_hsync_time(fbi, pcd); +- fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd); ++ fbi->reg_lccr3 = (fbi->reg_lccr3 & ~(LCCR3_PCD)) | LCCR3_PixClkDiv(pcd); ++ //W do we need to set LCCR4_PCDDIV here? + set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE); + break; + } +@@ -1403,6 +1412,9 @@ + if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas && + (inf->modes->upper_margin || inf->modes->lower_margin)) + dev_warn(&dev->dev, "Upper and lower margins must be 0 in passive mode\n"); ++ if ((inf->lccr4 & LCCR4_PCDDIV) && ((inf->lccr3 & LCCR3_PCD) < 1)) ++ dev_warn(&dev->dev, "Invalid pixel clock register settings\n"); ++ + #endif + + dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",inf->modes->xres, inf->modes->yres, inf->modes->bpp); +Index: linux-2.6.25.2/drivers/video/pxafb.h +=================================================================== +--- linux-2.6.25.2.orig/drivers/video/pxafb.h 2008-05-09 18:31:24.000000000 +0100 ++++ linux-2.6.25.2/drivers/video/pxafb.h 2008-05-09 18:31:24.000000000 +0100 +@@ -27,6 +27,7 @@ + unsigned int lccr1; + unsigned int lccr2; + unsigned int lccr3; ++ unsigned int lccr4; + }; + + /* PXA LCD DMA descriptor */ +Index: linux-2.6.25.2/include/asm-arm/arch-pxa/pxa-regs.h +=================================================================== +--- linux-2.6.25.2.orig/include/asm-arm/arch-pxa/pxa-regs.h 2008-05-09 18:31:24.000000000 +0100 ++++ linux-2.6.25.2/include/asm-arm/arch-pxa/pxa-regs.h 2008-05-09 18:31:24.000000000 +0100 +@@ -1677,7 +1677,8 @@ + #define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */ + #define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */ + #define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */ +-#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 3 */ ++#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 4 */ ++#define LCCR5 __REG(0x44000010) /* LCD Controller Control Register 5 */ + #define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ + #define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ + #define LCSR __REG(0x44000038) /* LCD Controller Status Register */ +@@ -1836,6 +1837,44 @@ + #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ + /* active Low */ + ++#define LCCR4_PCDDIV (1<<31) /* PCD Divisor Selection */ ++#define LCCR4_PAL_FOR Fld (2, 15) /* Palette Data Format */ ++#define LCCR4_PalFor(PalFor) (((PalFor << FShft(LCCR4_PAL_FOR))) ++#define LCCR4_K3 Fld (3,6) /* Multiplication constant for Green for Half Transparency */ ++#define LCCR4_K3green(K) (((K) << FShft (LCCR4_K3))) ++#define LCCR4_K2 Fld (3,3) /* Multiplication constant for Blue for Half Transparency */ ++#define LCCR4_K2blue(K) (((K) << FShft (LCCR4_K2))) ++#define LCCR4_K1 Fld (3,0) /* Multiplication constant for Red for Half Transparency */ ++#define LCCR4_K1red(K) (((K) << FShft (LCCR4_K1))) ++ ++#define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for Command Data */ ++#define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for Cursor */ ++#define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */ ++#define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */ ++#define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */ ++#define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */ ++ ++#define LCCR5_BSM6 (1<<21) /* Branch Mask for DMA Channel 6 */ ++#define LCCR5_BSM5 (1<<20) /* Branch Mask for DMA Channel 5 */ ++#define LCCR5_BSM4 (1<<19) /* Branch Mask for DMA Channel 4 */ ++#define LCCR5_BSM3 (1<<18) /* Branch Mask for DMA Channel 3 */ ++#define LCCR5_BSM2 (1<<17) /* Branch Mask for DMA Channel 2 */ ++#define LCCR5_BSM1 (1<<16) /* Branch Mask for DMA Channel 1 */ ++ ++#define LCCR5_EOFM6 (1<<13) /* End of Frame Mask for DMA Channel 6 */ ++#define LCCR5_EOFM5 (1<<12) /* End of Frame Mask for DMA Channel 5 */ ++#define LCCR5_EOFM4 (1<<11) /* End of Frame Mask for DMA Channel 4 */ ++#define LCCR5_EOFM3 (1<<10) /* End of Frame Mask for DMA Channel 3 */ ++#define LCCR5_EOFM2 (1<<9) /* End of Frame Mask for DMA Channel 2 */ ++#define LCCR5_EOFM1 (1<<8) /* End of Frame Mask for DMA Channel 1 */ ++ ++#define LCCR5_SOFM5 (1<<5) /* Start of Frame Mask for DMA Channel 6 */ ++#define LCCR5_SOFM4 (1<<4) /* Start of Frame Mask for DMA Channel 6 */ ++#define LCCR5_SOFM3 (1<<3) /* Start of Frame Mask for DMA Channel 6 */ ++#define LCCR5_SOFM2 (1<<2) /* Start of Frame Mask for DMA Channel 6 */ ++#define LCCR5_SOFM1 (1<<1) /* Start of Frame Mask for DMA Channel 6 */ ++#define LCCR5_SOFM0 (1<<0) /* Start of Frame Mask for DMA Channel 6 */ ++ + #define LCSR_LDD (1 << 0) /* LCD Disable Done */ + #define LCSR_SOF (1 << 1) /* Start of frame */ + #define LCSR_BER (1 << 2) /* Bus error */ +Index: linux-2.6.25.2/include/asm-arm/arch-pxa/pxafb.h +=================================================================== +--- linux-2.6.25.2.orig/include/asm-arm/arch-pxa/pxafb.h 2008-05-09 18:31:24.000000000 +0100 ++++ linux-2.6.25.2/include/asm-arm/arch-pxa/pxafb.h 2008-05-09 18:31:24.000000000 +0100 +@@ -72,8 +72,8 @@ + u_int lccr3; + /* The following should be defined in LCCR4 + * LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2 ++ * LCCR4_PCDDIV (if odd pixclock divisor required) + * +- * All other bits in LCCR4 should be left alone. + */ + u_int lccr4; + void (*pxafb_backlight_power)(int); +Index: linux-2.6.25.2/drivers/video/fbmem.c +=================================================================== +--- linux-2.6.25.2.orig/drivers/video/fbmem.c 2008-05-09 18:31:24.000000000 +0100 ++++ linux-2.6.25.2/drivers/video/fbmem.c 2008-05-09 18:31:24.000000000 +0100 +@@ -1008,6 +1008,8 @@ + return copy_to_user(argp, &info->var, + sizeof(var)) ? -EFAULT : 0; + case FBIOPUT_VSCREENINFO: ++ /*!! W - pretend it worked*/ ++ return 0; + if (copy_from_user(&var, argp, sizeof(var))) + return -EFAULT; + acquire_console_sem(); Added: balloon/trunk/kernel/2.6.25.2/balloon3.patch =================================================================== --- balloon/trunk/kernel/2.6.25.2/balloon3.patch (rev 0) +++ balloon/trunk/kernel/2.6.25.2/balloon3.patch 2008-05-11 01:24:31 UTC (rev 479) @@ -0,0 +1,776 @@ +Index: include/asm-arm/arch-pxa/debug-macro.S +=================================================================== +--- include/asm-arm/arch-pxa/debug-macro.S.orig 2008-05-09 18:09:23.000000000 +0100 ++++ include/asm-arm/arch-pxa/debug-macro.S 2008-05-09 18:09:28.000000000 +0100 +@@ -18,7 +18,11 @@ + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x40000000 @ physical + movne \rx, #io_p2v(0x40000000) @ virtual ++#if defined(CONFIG_MACH_BALLOON3) ++ orr \rx, \rx, #0x00700000 @ STUART ++#else + orr \rx, \rx, #0x00100000 ++#endif + .endm + + #define UART_SHIFT 2 +Index: include/asm-arm/arch-pxa/balloon3.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ include/asm-arm/arch-pxa/balloon3.h 2008-05-09 18:09:28.000000000 +0100 +@@ -0,0 +1,133 @@ ++/* ++ * linux/include/asm-arm/arch-pxa/balloon3.h ++ * ++ * Authors: Nick Bane and Wookey ++ * Created: Oct, 2005 ++ * Copyright: Toby Churchill Ltd ++ * Cribbed from mainstone.c, Nicholas Pitre, MontaVista Software Inc., Nov 14, 2002 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef ASM_ARCH_BALLOON3_H ++#define ASM_ARCH_BALLOON3_H ++ ++#define BALLOON3_FPGA_PHYS PXA_CS4_PHYS ++#define BALLOON3_FPGA_VIRT (0xf1000000) // as per balloon2 ++#define BALLOON3_FPGA_LENGTH 0x01000000 ++ ++#define BALLOON3_P2V(x) ((x) - BALLOON3_FPGA_PHYS + BALLOON3_FPGA_VIRT) ++#define BALLOON3_V2P(x) ((x) - BALLOON3_FPGA_VIRT + BALLOON3_FPGA_PHYS) ++ ++#ifndef __ASSEMBLY__ ++# define __BALLOON3_REG(x) (*((volatile unsigned long *)BALLOON3_P2V(x))) ++#else ++# define __BALLOON3_REG(x) BALLOON3_P2V(x) ++#endif ++ ++/* FPGA/CPLD registers */ ++#define BALLOON3_PCMCIA0_REG __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00e00008) ++#define BALLOON3_PCMCIA1_REG __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00e00008) /*fixme - same for now */ ++#define BALLOON3_NANDIO_IO_REG __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00e00000) ++#define BALLOON3_INT_CONTROL_REG __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00e0000C) /* fpga/cpld interrupt control register */ ++#define BALLOON3_NANDIO_CTL2_REG __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00e00010) ++#define BALLOON3_NANDIO_CTL_REG __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00e00014) ++#define BALLOON3_VERSION_REG __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00e0001c) ++ ++#define BALLOON3_SAMOSA_ADDR_REG __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00c00000) ++#define BALLOON3_SAMOSA_DATA_REG __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00c00004) ++#define BALLOON3_SAMOSA_STATUS_REG __BALLOON3_REG(BALLOON3_FPGA_PHYS+0x00c0001c) ++ ++/* GPIOs for irqs */ ++#define BALLOON3_GPIO_AUX_NIRQ (94) ++#define BALLOON3_GPIO_CODEC_IRQ (95) ++ ++/* Timer and Idle LED locations */ ++#define BALLOON3_GPIO_LED_TIMER (9) ++#define BALLOON3_GPIO_LED_IDLE (10) ++ ++/* backlight control */ ++#define BALLOON3_GPIO_RUN_BACKLIGHT (99) ++ ++ ++#define BALLOON3_GPIO_S0_CD (105) ++#define BALLOON3_GPIO_S1_CD (105) // FIXME clearly needs changing for real world ++ ++/*FPGA Interrupt Mask/Acknowledge Register */ ++#define BALLOON3_INT_S0_IRQ (1 << 0) /* PCMCIA socket 0 IRQ */ ++#define BALLOON3_INT_S0_STSCHG (1 << 1) /* PCMCIA socket 0 status changed */ ++ ++/*CF Status Register */ ++#define BALLOON3_PCMCIA_nIRQ (1 << 0) /* IRQ / ready signal */ ++#define BALLOON3_PCMCIA_nSTSCHG_BVD1 (1 << 1) /* VDD sense / card status changed */ ++ ++ ++/* CF control register (write) */ ++#define BALLOON3_PCMCIA_RESET (1 << 0) /* Card reset signal */ ++#define BALLOON3_PCMCIA_ENABLE (1 << 1) ++#define BALLOON3_PCMCIA_ADD_ENABLE (1 << 2) ++ ++/* CPLD (and FPGA) interface definitions */ ++#define CPLD_LCD0_DATA_SET 0x00 ++#define CPLD_LCD0_DATA_CLR 0x10 ++#define CPLD_LCD0_COMMAND_SET 0x01 ++#define CPLD_LCD0_COMMAND_CLR 0x11 ++#define CPLD_LCD1_DATA_SET 0x02 ++#define CPLD_LCD1_DATA_CLR 0x12 ++#define CPLD_LCD1_COMMAND_SET 0x03 ++#define CPLD_LCD1_COMMAND_CLR 0x13 ++ ++#define CPLD_MISC_SET 0x07 ++#define CPLD_MISC_CLR 0x17 ++#define CPLD_MISC_LOON_NRESET_BIT 0 ++#define CPLD_MISC_LOON_UNSUSP_BIT 1 ++#define CPLD_MISC_RUN_5V_BIT 2 ++#define CPLD_MISC_CHG_D0_BIT 3 ++#define CPLD_MISC_CHG_D1_BIT 4 ++#define CPLD_MISC_DAC_NCS_BIT 5 ++ ++#define CPLD_LCD_SET 0x08 ++#define CPLD_LCD_CLR 0x18 ++#define CPLD_LCD_BACKLIGHT_EN_0_BIT 0 ++#define CPLD_LCD_BACKLIGHT_EN_1_BIT 1 ++#define CPLD_LCD_LED_RED_BIT 4 ++#define CPLD_LCD_LED_GREEN_BIT 5 ++#define CPLD_LCD_NRESET_BIT 7 ++ ++#define CPLD_LCD_RO_SET 0x09 ++#define CPLD_LCD_RO_CLR 0x19 ++#define CPLD_LCD_RO_LCD0_nWAIT_BIT 0 ++#define CPLD_LCD_RO_LCD1_nWAIT_BIT 1 ++ ++#define CPLD_SERIAL_SET 0x0a ++#define CPLD_SERIAL_CLR 0x1a ++#define CPLD_SERIAL_GSM_RI_BIT 0 ++#define CPLD_SERIAL_GSM_CTS_BIT 1 ++#define CPLD_SERIAL_GSM_DTR_BIT 2 ++#define CPLD_SERIAL_LPR_CTS_BIT 3 ++#define CPLD_SERIAL_TC232_CTS_BIT 4 ++#define CPLD_SERIAL_TC232_DSR_BIT 5 ++ ++#define CPLD_SROUTING_SET 0x0b ++#define CPLD_SROUTING_CLR 0x1b ++#define CPLD_SROUTING_MSP430_LPR 0 ++#define CPLD_SROUTING_MSP430_TC232 1 ++#define CPLD_SROUTING_MSP430_GSM 2 ++#define CPLD_SROUTING_LOON_LPR (0 << 4) ++#define CPLD_SROUTING_LOON_TC232 (1 << 4) ++#define CPLD_SROUTING_LOON_GSM (2 << 4) ++ ++#define CPLD_AROUTING_SET 0x0c ++#define CPLD_AROUTING_CLR 0x1c ++#define CPLD_AROUTING_MIC2PHONE_BIT 0 ++#define CPLD_AROUTING_PHONE2INT_BIT 1 ++#define CPLD_AROUTING_PHONE2EXT_BIT 2 ++#define CPLD_AROUTING_LOONL2INT_BIT 3 ++#define CPLD_AROUTING_LOONL2EXT_BIT 4 ++#define CPLD_AROUTING_LOONR2PHONE_BIT 5 ++#define CPLD_AROUTING_LOONR2INT_BIT 6 ++#define CPLD_AROUTING_LOONR2EXT_BIT 7 ++ ++#endif +Index: include/asm-arm/arch-pxa/irqs.h +=================================================================== +--- include/asm-arm/arch-pxa/irqs.h.orig 2008-05-09 18:09:23.000000000 +0100 ++++ include/asm-arm/arch-pxa/irqs.h 2008-05-09 18:09:28.000000000 +0100 +@@ -181,7 +181,8 @@ + #elif defined(CONFIG_ARCH_LUBBOCK) || \ + defined(CONFIG_MACH_LOGICPD_PXA270) || \ + defined(CONFIG_MACH_MAINSTONE) || \ +- defined(CONFIG_MACH_PCM027) ++ defined(CONFIG_MACH_PCM027) || \ ++ defined(CONFIG_MACH_BALLOON3) + #define NR_IRQS (IRQ_BOARD_END) + #else + #define NR_IRQS (IRQ_BOARD_START) +@@ -222,6 +223,39 @@ + #define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) + #define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) + ++/* Balloon3 Interrupts */ ++#define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x)) ++ ++#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0) ++#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1) ++#define BALLOON3_BP_CD_IRQ BALLOON3_IRQ(2) ++ ++#define BALLOON3_AUX_NIRQ IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ) ++#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ) ++#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) ++#define BALLOON3_S1_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S1_CD) ++ ++#if 0 ++#define BALLOON3_MMC_IRQ BALLOON3_IRQ(0) ++#define BALLOON3_USIM_IRQ BALLOON3_IRQ(1) ++#define BALLOON3_USBC_IRQ BALLOON3_IRQ(2) ++#define BALLOON3_ETHERNET_IRQ BALLOON3_IRQ(3) ++#define BALLOON3_AC97_IRQ BALLOON3_IRQ(4) ++#define BALLOON3_PEN_IRQ BALLOON3_IRQ(5) ++#define BALLOON3_MSINS_IRQ BALLOON3_IRQ(6) ++#define BALLOON3_EXBRD_IRQ BALLOON3_IRQ(7) ++ ++//#define BALLOON3_S0_CD_IRQ BALLOON3_IRQ(9) ++#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_S0_CD) ++#define BALLOON3_S0_STSCHG_IRQ BALLOON3_IRQ(10) ++#define BALLOON3_S0_IRQ BALLOON3_IRQ(11) ++ ++//#define BALLOON3_S1_CD_IRQ BALLOON3_IRQ(13) ++#define BALLOON3_S1_CD_IRQ IRQ_GPIO(BALLOON3_S1_CD) ++#define BALLOON3_S1_STSCHG_IRQ BALLOON3_IRQ(14) ++#define BALLOON3_S1_IRQ BALLOON3_IRQ(15) ++#endif ++ + /* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */ + #define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0) + #define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) +Index: include/asm-arm/arch-pxa/uncompress.h +=================================================================== +--- include/asm-arm/arch-pxa/uncompress.h.orig 2008-05-09 18:09:23.000000000 +0100 ++++ include/asm-arm/arch-pxa/uncompress.h 2008-05-09 18:09:28.000000000 +0100 +@@ -14,7 +14,11 @@ + + #define __REG(x) ((volatile unsigned long *)x) + ++#ifdef CONFIG_MACH_BALLOON3 ++#define UART STUART ++#else + #define UART FFUART ++#endif + + + static inline void putc(char c) +Index: arch/arm/mach-pxa/Kconfig +=================================================================== +--- arch/arm/mach-pxa/Kconfig.orig 2008-05-09 18:09:23.000000000 +0100 ++++ arch/arm/mach-pxa/Kconfig 2008-05-09 18:09:28.000000000 +0100 +@@ -36,6 +36,11 @@ + bool "Intel HCDDBBVA0 Development Platform" + select PXA27x + ++config MACH_BALLOON3 ++ bool "Balloon 3 board" ++ select PXA27x ++ select IWMMXT ++ + config ARCH_PXA_IDP + bool "Accelent Xscale IDP" + select PXA25x +@@ -143,6 +148,14 @@ + + endchoice + ++if MACH_BALLOON3 ++config BALLOON3_TOPPOLY ++ bool "Toppoly LCD panel on Balloon3" ++ help ++ Say Y to add support for the Toppoly ++ QVGA/VGA LCD display on a Balloon3 board ++endif ++ + if PXA_SHARPSL + + choice +Index: arch/arm/mach-pxa/balloon3.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ arch/arm/mach-pxa/balloon3.c 2008-05-09 18:12:07.000000000 +0100 +@@ -0,0 +1,476 @@ ++/* ++ * linux/arch/arm/mach-pxa/balloon3.c ++ * ++ * Support for Balloonboard.org Balloon3 board. ++ * ++ * Author: Nick Bane ++ * Created: June, 2006 ++ * Copyright: Toby Churchill Ltd ++ * Derived from mainstone.c, by Nico Pitre ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "generic.h" ++ ++#define putstr(x) printk(x) ++ ++static unsigned long balloon3_irq_enabled; ++ ++static void balloon3_mask_irq(unsigned int irq) ++{ ++ int balloon3_irq = (irq - BALLOON3_IRQ(0)); ++ balloon3_irq_enabled &= ~(1 << balloon3_irq); ++ BALLOON3_INT_CONTROL_REG = ~balloon3_irq_enabled ; ++//printk("%s: irq %d\n",__FUNCTION__,irq); ++} ++ ++static void balloon3_ack_irq(unsigned int irq) ++{ ++// printk("int ack %d\n", irq); ++ balloon3_mask_irq(irq); ++} ++ ++static void balloon3_unmask_irq(unsigned int irq) ++{ ++ int balloon3_irq = (irq - BALLOON3_IRQ(0)); ++ balloon3_irq_enabled |= (1 << balloon3_irq); ++ BALLOON3_INT_CONTROL_REG = ~balloon3_irq_enabled ; ++//printk("%s: irq=%d, pending =0x%lx\n",__FUNCTION__, irq, BALLOON3_INT_CONTROL_REG & balloon3_irq_enabled); ++} ++ ++static struct irq_chip balloon3_irq_chip = { ++ .name = "FPGA", ++ .ack = balloon3_ack_irq, ++ .mask = balloon3_mask_irq, ++ .unmask = balloon3_unmask_irq, ++}; ++ ++static void balloon3_irq_handler(unsigned int irq, struct irq_desc *desc) ++{ ++ unsigned long pending = BALLOON3_INT_CONTROL_REG & balloon3_irq_enabled; ++//printk("%s: pending without mask=0x%lx, mask=0x%lx with mask=0x%lx\n",__FUNCTION__, ++// BALLOON3_INT_CONTROL_REG, balloon3_irq_enabled, pending); ++ do { ++ GEDR(BALLOON3_GPIO_AUX_NIRQ) = GPIO_bit(BALLOON3_GPIO_AUX_NIRQ); /* clear useless edge notification */ ++ if (likely(pending)) { ++ irq = BALLOON3_IRQ(0) + __ffs(pending); ++ desc = irq_desc + irq; ++ desc_handle_irq(irq, desc); ++ } ++ pending = BALLOON3_INT_CONTROL_REG & balloon3_irq_enabled; ++ } while (pending); ++} ++ ++static void __init balloon3_init_irq(void) ++{ ++ int irq; ++ ++ pxa27x_init_irq(); ++ /* setup extra Balloon3 irqs */ ++ for(irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(15); irq++) { ++ set_irq_chip(irq, &balloon3_irq_chip); ++ set_irq_handler(irq, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); ++ } ++ ++ set_irq_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler); ++ set_irq_type(BALLOON3_AUX_NIRQ, IRQT_FALLING); ++ ++printk("%s: chained handler installed - irq %d automatically enabled\n",__FUNCTION__,BALLOON3_AUX_NIRQ); ++} ++ ++#ifdef CONFIG_PM ++ ++static int balloon3_irq_resume(struct sys_device *dev) ++{ ++ // eneable something in CPLD/FPGA here? ++#if 0 ++ MST_INTMSKENA = balloon3_irq_enabled; ++#endif ++ return 0; ++} ++ ++static struct sysdev_class balloon3_irq_sysclass = { ++ .name = "cpld_irq", ++ .resume = balloon3_irq_resume, ++}; ++ ++static struct sys_device balloon3_irq_device = { ++ .cls = &balloon3_irq_sysclass, ++}; ++ ++static int __init balloon3_irq_device_init(void) ++{ ++ int ret = sysdev_class_register(&balloon3_irq_sysclass); ++ if (ret == 0) ++ ret = sysdev_register(&balloon3_irq_device); ++ return ret; ++} ++ ++device_initcall(balloon3_irq_device_init); ++ ++#endif ++ ++#if 0 //FIXME: "expected ‘)’ before ‘*’ token" ++static int balloon3_audio_startup(snd_pcm_substream_t *substream, void *priv) ++{ ++#if 0 ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF; ++#endif ++ return 0; ++} ++ ++static void balloon3_audio_shutdown(snd_pcm_substream_t *substream, void *priv) ++{ ++#if 0 ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF; ++#endif ++} ++#endif ++ ++//static long balloon3_audio_suspend_mask; ++ ++static void balloon3_audio_suspend(void *priv) ++{ ++#if 0 ++ balloon3_audio_suspend_mask = MST_MSCWR2; ++ MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF; ++#endif ++} ++ ++static void balloon3_audio_resume(void *priv) ++{ ++#if 0 ++ MST_MSCWR2 &= mst_audio_suspend_mask | ~MST_MSCWR2_AC97_SPKROFF; ++#endif ++} ++ ++static pxa2xx_audio_ops_t balloon3_audio_ops = { ++// .startup = balloon3_audio_startup, ++// .shutdown = balloon3_audio_shutdown, ++ .suspend = balloon3_audio_suspend, ++ .resume = balloon3_audio_resume, ++}; ++ ++static struct platform_device balloon3_audio_device = { ++ .name = "pxa2xx-ac97", ++ .id = -1, ++ .dev = { .platform_data = &balloon3_audio_ops }, ++}; ++ ++ ++static void balloon3_backlight_power(int on) ++{ ++#ifdef CONFIG_BALLOON3_TOPPOLY ++ // balloon 3 backlight control is on GPIO99, and it's already set up ++ // as an output by bootldr in theory, but we set the pin as an output ++ // just in case ++ if (on) { ++ printk("%s: power is on\n",__FUNCTION__); ++ pxa_gpio_mode(BALLOON3_GPIO_RUN_BACKLIGHT | GPIO_OUT); ++ GPSR(BALLOON3_GPIO_RUN_BACKLIGHT) = GPIO_bit(BALLOON3_GPIO_RUN_BACKLIGHT); ++ } ++ else { ++ printk("%s: power is off\n",__FUNCTION__); ++ pxa_gpio_mode(BALLOON3_GPIO_RUN_BACKLIGHT | GPIO_OUT); ++ GPCR(BALLOON3_GPIO_RUN_BACKLIGHT) = GPIO_bit(BALLOON3_GPIO_RUN_BACKLIGHT); ++ } ++#endif ++} ++ ++#ifdef CONFIG_BALLOON3_TOPPOLY ++static struct pxafb_mode_info toppoly_mode __initdata = { ++ .pixclock = 38000, ++ .xres = 480, ++ .yres = 640, ++ .bpp = 16, ++ .hsync_len = 8, ++ .left_margin = 8, ++ .right_margin = 8, ++ .vsync_len = 2, ++ .upper_margin = 4, ++ .lower_margin = 5, ++ .sync = 0, ++}; ++ ++static struct pxafb_mach_info balloon3_pxafb_info = { ++ .num_modes = 1, ++ .lccr0 = LCCR0_Act, ++ .lccr3 = LCCR3_PCP, ++ .pxafb_backlight_power = balloon3_backlight_power, ++}; ++ ++#endif ++ ++static int balloon3_mci_init(struct device *dev, irq_handler_t balloon3_detect_int, void *data) ++{ ++ ++ /* ++ * setup GPIO for PXA27x MMC controller ++ */ ++ pxa_gpio_mode(GPIO32_MMCCLK_MD); ++ pxa_gpio_mode(GPIO112_MMCCMD_MD); ++ pxa_gpio_mode(GPIO92_MMCDAT0_MD); ++ pxa_gpio_mode(GPIO109_MMCDAT1_MD); ++ pxa_gpio_mode(GPIO110_MMCDAT2_MD); ++ pxa_gpio_mode(GPIO111_MMCDAT3_MD); ++ ++ ++ return 0; ++} ++ ++static void balloon3_mci_setpower(struct device *dev, unsigned int vdd) ++{ ++ ++#if 0 ++ struct pxamci_platform_data* p_d = dev->platform_data; ++ if (( 1 << vdd) & p_d->ocr_mask) { ++ printk(KERN_DEBUG "%s: on\n", __FUNCTION__); ++ MST_MSCWR1 |= MST_MSCWR1_MMC_ON; ++ MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL; ++ } else { ++ printk(KERN_DEBUG "%s: off\n", __FUNCTION__); ++ MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON; ++ } ++#endif ++} ++ ++static void balloon3_mci_exit(struct device *dev, void *data) ++{ ++// free_irq(BALLOON3_MMC_IRQ, data); ++} ++ ++static struct pxamci_platform_data balloon3_mci_platform_data = { ++ .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, ++ .init = balloon3_mci_init, ++ .setpower = balloon3_mci_setpower, ++ .exit = balloon3_mci_exit, ++}; ++ ++static void balloon3_irda_transceiver_mode(struct device *dev, int mode) ++{ ++#if 0 ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ if (mode & IR_SIRMODE) { ++ MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR; ++ } else if (mode & IR_FIRMODE) { ++ MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR; ++ } ++ if (mode & IR_OFF) { ++ MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF; ++ } else { ++ MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_FULL; ++ } ++ local_irq_restore(flags); ++#endif ++} ++ ++static int balloon3_udc_is_connected(void) ++{ ++#if 1 ++ pr_debug("%s:\n", __FUNCTION__); ++ return 1; ++#else ++ ((MST_MSCRD & MST_MSCRD_USB_CBL) != 0)); ++ return (MST_MSCRD & MST_MSCRD_USB_CBL) != 0; ++#endif ++} ++ ++static void balloon3_udc_command(int cmd) ++{ ++ switch (cmd) { ++ case PXA2XX_UDC_CMD_CONNECT: ++ UP2OCR|=(UP2OCR_DPPUE + UP2OCR_DPPUBE); ++ pr_debug("%s: connect\n", __FUNCTION__); ++ break; ++ case PXA2XX_UDC_CMD_DISCONNECT: ++ UP2OCR&=~UP2OCR_DPPUE; ++ pr_debug("%s: disconnect\n", __FUNCTION__); ++ break; ++ } ++ ++} ++ ++static struct pxa2xx_udc_mach_info balloon3_udc_info = { ++ .udc_is_connected = balloon3_udc_is_connected, ++ .udc_command = balloon3_udc_command, ++}; ++ ++ ++static struct pxaficp_platform_data balloon3_ficp_platform_data = { ++ .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF, ++ .transceiver_mode = balloon3_irda_transceiver_mode, ++}; ++ ++static struct platform_device *platform_devices[] __initdata = { ++ &balloon3_audio_device, ++// &mst_flash_device[0], ++// &mst_flash_device[1], ++}; ++ ++static int balloon3_ohci_init(struct device *dev) ++{ ++ /* setup Port1 GPIO pin. */ ++ pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */ ++ pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */ ++ ++ /* Set the Power Control Polarity Low and Power Sense ++ Polarity Low to active low. */ ++ UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & ++ ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE); ++ ++ printk("*** ohci_init\r\n"); ++ /* set USB Host port 2 to use external transceiver */ ++ UP2OCR&=~(7<<24); ++ UP2OCR|=(5<<24); ++ /* switch on power to USB host port 2 */ ++ /* by setting GPIO100 low */ ++ GPCR3=GPIO_bit(100); ++ ++ return 0; ++} ++ ++static struct pxaohci_platform_data balloon3_ohci_platform_data = { ++ .port_mode = PMM_PERPORT_MODE, ++ .init = balloon3_ohci_init, ++}; ++ ++static void __init balloon3_init(void) ++{ ++// int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */ ++ ++putstr("Running balloon3_init()\n"); ++ ++ /* system bus arbiter setting ++ * - Core_Park ++ * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4 ++ */ ++ ARB_CNTRL = ARB_CORE_PARK | 0x234; ++ ++#if 0 ++ /* ++ * On Mainstone, we route AC97_SYSCLK via GPIO45 to ++ * the audio daughter card ++ */ ++ //on balloon3 its on gpio28 ++ pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD); ++#endif ++ ++ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); ++ ++#ifdef CONFIG_BALLOON3_TOPPOLY ++ balloon3_pxafb_info.modes = &toppoly_mode; ++ set_pxa_fb_info(&balloon3_pxafb_info); ++#endif ++ ++ pxa_set_mci_info(&balloon3_mci_platform_data); ++ pxa_set_ficp_info(&balloon3_ficp_platform_data); ++ pxa_set_ohci_info(&balloon3_ohci_platform_data); ++ pxa_set_udc_info(&balloon3_udc_info); ++} ++ ++static struct map_desc balloon3_io_desc[] __initdata = { ++ { /* CPLD */ ++ .virtual = BALLOON3_FPGA_VIRT, ++ .pfn = __phys_to_pfn(BALLOON3_FPGA_PHYS), ++ .length = BALLOON3_FPGA_LENGTH, ++ .type = MT_DEVICE ++ } ++}; ++ ++static void __init balloon3_map_io(void) ++{ ++putstr("Running balloon3_map_io()\n"); ++putstr("calling pxa_map_io()\n"); ++ pxa_map_io(); ++putstr("pxa_map_io() done\n"); ++ iotable_init(balloon3_io_desc, ARRAY_SIZE(balloon3_io_desc)); ++putstr("iotable_init() done\n"); ++ ++ /* Select BTUART 'COM1/ttyS0' as IO option for pins 42/43/44/45 */ ++ pxa_gpio_mode(GPIO42_BTRXD_MD); ++ pxa_gpio_mode(GPIO43_BTTXD_MD); ++ /* CTS and RTS _could_ be spare GPIOs if not needed here or by bluetooth - CONFIG option? */ ++ pxa_gpio_mode(GPIO44_BTCTS_MD); ++ pxa_gpio_mode(GPIO45_BTRTS_MD); ++ ++#if 0 ++ ++ /* initialize sleep mode regs (wake-up sources, etc) */ ++ PGSR0 = 0x00008800; ++ PGSR1 = 0x00000002; ++ PGSR2 = 0x0001FC00; ++ PGSR3 = 0x00001F81; ++#endif ++ PWER = 0xC0000002; ++ PRER = 0x00000002; ++ PFER = 0x00000002; ++#if 0 ++ /* for use I SRAM as framebuffer. */ ++ PSLR |= 0xF04; ++ PCFR = 0x66; ++ /* For Keypad wakeup. */ ++ KPC &=~KPC_ASACT; ++ KPC |=KPC_AS; ++ PKWR = 0x000FD000; ++ /* Need read PKWR back after set it. */ ++ PKWR; ++#endif ++} ++ ++MACHINE_START(BALLOON3, "Balloon3") ++ /* Maintainer: Nick Bane. */ ++ .phys_io = 0x40000000, ++ ++ // added NCB for -21-rc7-tcl1 ++ .boot_params = 0xa0000100, /* BLOB boot parameter setting */ ++ ++ .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, ++ .map_io = balloon3_map_io, ++ .init_irq = balloon3_init_irq, ++ .timer = &pxa_timer, ++ .init_machine = balloon3_init, ++ ++ .boot_params = PHYS_OFFSET+0x100, ++MACHINE_END +Index: arch/arm/Kconfig +=================================================================== +--- arch/arm/Kconfig.orig 2008-05-09 18:09:23.000000000 +0100 ++++ arch/arm/Kconfig 2008-05-09 18:09:28.000000000 +0100 +@@ -790,7 +790,7 @@ + ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ + ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \ + ARCH_AT91 || MACH_TRIZEPS4 || ARCH_DAVINCI || \ +- ARCH_KS8695 || MACH_RD88F5182 ++ ARCH_KS8695 || MACH_RD88F5182 || MACH_BALLOON3 + help + If you say Y here, the LEDs on your machine will be used + to provide useful information about your current system status. +Index: arch/arm/mach-pxa/Makefile +=================================================================== +--- arch/arm/mach-pxa/Makefile.orig 2008-05-09 18:09:23.000000000 +0100 ++++ arch/arm/mach-pxa/Makefile 2008-05-09 18:09:28.000000000 +0100 +@@ -15,6 +15,7 @@ + obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o + obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o + obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o ++obj-$(CONFIG_MACH_BALLOON3) += balloon3.o + obj-$(CONFIG_ARCH_PXA_IDP) += idp.o + obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o + obj-$(CONFIG_MACH_COLIBRI) += colibri.o +Index: Makefile +=================================================================== +--- Makefile.orig 2008-05-09 18:09:23.000000000 +0100 ++++ Makefile 2008-05-09 18:09:28.000000000 +0100 +@@ -190,8 +190,8 @@ + # Default value for CROSS_COMPILE is not to prefix executables + # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile + export KBUILD_BUILDHOST := $(SUBARCH) +-ARCH ?= $(SUBARCH) +-CROSS_COMPILE ?= ++ARCH ?= arm ++#CROSS_COMPILE ?= + + # Architecture as present in compile.h + UTS_MACHINE := $(ARCH) Added: balloon/trunk/kernel/2.6.25.2/balloon3config-add-wlan-modules.patch =================================================================== --- balloon/trunk/kernel/2.6.25.2/balloon3config-add-wlan-modules.patch (rev 0) +++ balloon/trunk/kernel/2.6.25.2/balloon3config-add-wlan-modules.patch 2008-05-11 01:24:31 UTC (rev 479) @@ -0,0 +1,23 @@ +Index: linux-2.6.25.2/arch/arm/configs/balloon3_defconfig +=================================================================== +--- linux-2.6.25.2.orig/arch/arm/configs/balloon3_defconfig 2008-05-09 17:22:12.000000000 +0100 ++++ linux-2.6.25.2/arch/arm/configs/balloon3_defconfig 2008-05-09 17:22:17.000000000 +0100 +@@ -762,13 +762,16 @@ + CONFIG_WLAN_80211=y + CONFIG_PCMCIA_RAYCS=m + CONFIG_LIBERTAS=m ++CONFIG_LIBERTAS_USB=m ++CONFIG_LIBERTAS_CS=m + CONFIG_HERMES=m + CONFIG_ATMEL=m + CONFIG_AIRO_CS=m + CONFIG_PCMCIA_WL3501=m +-# CONFIG_USB_ZD1201 is not set ++CONFIG_USB_ZD1201=m + CONFIG_HOSTAP=m +-# CONFIG_HOSTAP_FIRMWARE is not set ++CONFIG_HOSTAP_FIRMWARE=y ++CONFIG_HOSTAP_FIRMWARE_NVRAM=y + CONFIG_HOSTAP_CS=m + + # Added: balloon/trunk/kernel/2.6.25.2/balloon3config.patch =================================================================== --- balloon/trunk/kernel/2.6.25.2/balloon3config.patch (rev 0) +++ balloon/trunk/kernel/2.6.25.2/balloon3config.patch 2008-05-11 01:24:31 UTC (rev 479) @@ -0,0 +1,1940 @@ +Index: linux-2.6.22.2/arch/arm/configs/balloon3_defconfig +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-2.6.22.2/arch/arm/configs/balloon3_defconfig 2008-05-01 02:34:06.000000000 +0100 +@@ -0,0 +1,1935 @@ ++# ++# Automatically generated make config: don't edit ++# Linux kernel version: 2.6.22.2 ++# Thu Sep 6 02:36:23 2007 ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++CONFIG_GENERIC_TIME=y ++# CONFIG_GENERIC_CLOCKEVENTS is not set ++CONFIG_MMU=y ++# CONFIG_NO_IOPORT is not set ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++# CONFIG_ARCH_HAS_ILOG2_U32 is not set ++# CONFIG_ARCH_HAS_ILOG2_U64 is not set ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_ARCH_MTD_XIP=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++ ++# ++# Code maturity level options ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++ ++# ++# General setup ++# ++CONFIG_LOCALVERSION="-pxa270" ++CONFIG_LOCALVERSION_AUTO=y ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++# CONFIG_IPC_NS is not set ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_UTS_NS is not set ++# CONFIG_AUDIT is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=14 ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++# CONFIG_EMBEDDED is not set ++CONFIG_UID16=y ++CONFIG_SYSCTL_SYSCALL=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_ALL is not set ++# CONFIG_KALLSYMS_EXTRA_PASS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_ANON_INODES=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++CONFIG_RT_MUTEXES=y ++# CONFIG_TINY_SHMEM is not set ++CONFIG_BASE_SMALL=0 ++ ++# ++# Loadable module support ++# ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++CONFIG_KMOD=y ++ ++# ++# Block layer ++# ++CONFIG_BLOCK=y ++# CONFIG_LBD is not set ++# CONFIG_BLK_DEV_IO_TRACE is not set ++# CONFIG_LSF is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_AS=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++CONFIG_DEFAULT_AS=y ++# CONFIG_DEFAULT_DEADLINE is not set ++# CONFIG_DEFAULT_CFQ is not set ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="anticipatory" ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AAEC2000 is not set ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS7500 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_CO285 is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_L7200 is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_NS9XXX is not set ++# CONFIG_ARCH_PNX4008 is not set ++CONFIG_ARCH_PXA=y ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_LH7A40X is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++ ++# ++# Intel PXA2xx Implementations ++# ++# CONFIG_ARCH_LUBBOCK is not set ++# CONFIG_MACH_LOGICPD_PXA270 is not set ++# CONFIG_MACH_MAINSTONE is not set ++CONFIG_MACH_BALLOON3=y ++# CONFIG_ARCH_PXA_IDP is not set ++# CONFIG_PXA_SHARPSL is not set ++# CONFIG_MACH_TRIZEPS4 is not set ++CONFIG_BALLOON3_TOPPOLY=y ++# CONFIG_BALLOON3_VGA is not set ++# CONFIG_BALLOON3_SVGA is not set ++CONFIG_PXA27x=y ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_XSCALE=y ++CONFIG_CPU_32v5=y ++CONFIG_CPU_ABRT_EV5T=y ++CONFIG_CPU_CACHE_VIVT=y ++CONFIG_CPU_TLB_V4WBI=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_THUMB is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_OUTER_CACHE is not set ++CONFIG_IWMMXT=y ++CONFIG_XSCALE_PMU=y ++ ++# ++# Bus support ++# ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++ ++# ++# PCCARD (PCMCIA/CardBus) support ++# ++CONFIG_PCCARD=m ++CONFIG_PCMCIA_DEBUG=y ++CONFIG_PCMCIA=m ++CONFIG_PCMCIA_LOAD_CIS=y ++# CONFIG_PCMCIA_IOCTL is not set ++ ++# ++# PC-card bridges ++# ++CONFIG_PCMCIA_PXA2XX=m ++ ++# ++# Kernel Features ++# ++# CONFIG_TICK_ONESHOT is not set ++# CONFIG_PREEMPT is not set ++CONFIG_NO_IDLE_HZ=y ++CONFIG_HZ=100 ++# CONFIG_AEABI is not set ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++# CONFIG_DISCONTIGMEM_MANUAL is not set ++# CONFIG_SPARSEMEM_MANUAL is not set ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++# CONFIG_SPARSEMEM_STATIC is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4096 ++# CONFIG_RESOURCES_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_LEDS=y ++CONFIG_LEDS_TIMER=y ++CONFIG_LEDS_CPU=y ++CONFIG_ALIGNMENT_TRAP=y ++ ++# ++# Boot options ++# ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_FPE_NWFPE=y ++# CONFIG_FPE_NWFPE_XP is not set ++# CONFIG_FPE_FASTFPE is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++CONFIG_PM=y ++CONFIG_PM_LEGACY=y ++CONFIG_PM_DEBUG=y ++CONFIG_DISABLE_CONSOLE_SUSPEND=y ++CONFIG_PM_SYSFS_DEPRECATED=y ++CONFIG_AP_MEMULATION= ++y ++ ++# ++# Networking ++# ++CONFIG_NET=y ++CONFIG_NETDEVICES=y ++CONFIG_TUN=m ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=m ++CONFIG_NET_PCI=y ++CONFIG_CS89x0=m ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++CONFIG_PACKET_MMAP=y ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_ASK_IP_FIB_HASH=y ++# CONFIG_IP_FIB_TRIE is not set ++CONFIG_IP_FIB_HASH=y ++CONFIG_IP_MULTIPLE_TABLES=y ++# CONFIG_IP_ROUTE_MULTIPATH is not set ++# CONFIG_IP_ROUTE_VERBOSE is not set ++# CONFIG_IP_PNP is not set ++CONFIG_NET_IPIP=m ++CONFIG_NET_IPGRE=m ++# CONFIG_NET_IPGRE_BROADCAST is not set ++# CONFIG_IP_MROUTE is not set ++# CONFIG_ARPD is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++CONFIG_INET_TUNNEL=m ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IP_VS is not set ++CONFIG_IPV6=m ++# CONFIG_IPV6_PRIVACY is not set ++# CONFIG_IPV6_ROUTER_PREF is not set ++# CONFIG_IPV6_OPTIMISTIC_DAD is not set ++# CONFIG_INET6_AH is not set ++# CONFIG_INET6_ESP is not set ++# CONFIG_INET6_IPCOMP is not set ++# CONFIG_IPV6_MIP6 is not set ++# CONFIG_INET6_XFRM_TUNNEL is not set ++# CONFIG_INET6_TUNNEL is not set ++CONFIG_INET6_XFRM_MODE_TRANSPORT=m ++CONFIG_INET6_XFRM_MODE_TUNNEL=m ++CONFIG_INET6_XFRM_MODE_BEET=m ++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set ++CONFIG_IPV6_SIT=m ++# CONFIG_IPV6_TUNNEL is not set ++# CONFIG_IPV6_MULTIPLE_TABLES is not set ++# CONFIG_NETWORK_SECMARK is not set ++CONFIG_NETFILTER=y ++# CONFIG_NETFILTER_DEBUG is not set ++# CONFIG_BRIDGE_NETFILTER is not set ++ ++# ++# Core Netfilter Configuration ++# ++CONFIG_NETFILTER_NETLINK=m ++# CONFIG_NETFILTER_NETLINK_QUEUE is not set ++# CONFIG_NETFILTER_NETLINK_LOG is not set ++# CONFIG_NF_CONNTRACK_ENABLED is not set ++# CONFIG_NF_CONNTRACK is not set ++# CONFIG_NETFILTER_XTABLES is not set ++ ++# ++# IP: Netfilter Configuration ++# ++CONFIG_IP_NF_QUEUE=m ++# CONFIG_IP_NF_IPTABLES is not set ++# CONFIG_IP_NF_ARPTABLES is not set ++ ++# ++# IPv6: Netfilter Configuration (EXPERIMENTAL) ++# ++CONFIG_IP6_NF_QUEUE=m ++# CONFIG_IP6_NF_IPTABLES is not set ++ ++# ++# Bridge: Netfilter Configuration ++# ++CONFIG_BRIDGE_NF_EBTABLES=m ++CONFIG_BRIDGE_EBT_BROUTE=m ++CONFIG_BRIDGE_EBT_T_FILTER=m ++CONFIG_BRIDGE_EBT_T_NAT=m ++CONFIG_BRIDGE_EBT_802_3=m ++CONFIG_BRIDGE_EBT_AMONG=m ++CONFIG_BRIDGE_EBT_ARP=m ++CONFIG_BRIDGE_EBT_IP=m ++CONFIG_BRIDGE_EBT_LIMIT=m ++CONFIG_BRIDGE_EBT_MARK=m ++CONFIG_BRIDGE_EBT_PKTTYPE=m ++CONFIG_BRIDGE_EBT_STP=m ++CONFIG_BRIDGE_EBT_VLAN=m ++CONFIG_BRIDGE_EBT_ARPREPLY=m ++CONFIG_BRIDGE_EBT_DNAT=m ++CONFIG_BRIDGE_EBT_MARK_T=m ++CONFIG_BRIDGE_EBT_REDIRECT=m ++CONFIG_BRIDGE_EBT_SNAT=m ++CONFIG_BRIDGE_EBT_LOG=m ++CONFIG_BRIDGE_EBT_ULOG=m ++# CONFIG_IP_DCCP is not set ++CONFIG_IP_SCTP=m ++# CONFIG_SCTP_DBG_MSG is not set ++# CONFIG_SCTP_DBG_OBJCNT is not set ++# CONFIG_SCTP_HMAC_NONE is not set ++# CONFIG_SCTP_HMAC_SHA1 is not set ++CONFIG_SCTP_HMAC_MD5=y ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++CONFIG_BRIDGE=m ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++CONFIG_LLC=m ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++ ++# ++# QoS and/or fair queueing ++# ++CONFIG_NET_SCHED=y ++CONFIG_NET_SCH_FIFO=y ++ ++# ++# Queueing/Scheduling ++# ++# CONFIG_NET_SCH_CBQ is not set ++# CONFIG_NET_SCH_HTB is not set ++# CONFIG_NET_SCH_HFSC is not set ++# CONFIG_NET_SCH_PRIO is not set ++# CONFIG_NET_SCH_RED is not set ++# CONFIG_NET_SCH_SFQ is not set ++# CONFIG_NET_SCH_TEQL is not set ++# CONFIG_NET_SCH_TBF is not set ++# CONFIG_NET_SCH_GRED is not set ++# CONFIG_NET_SCH_DSMARK is not set ++# CONFIG_NET_SCH_NETEM is not set ++# CONFIG_NET_SCH_INGRESS is not set ++ ++# ++# Classification ++# ++# CONFIG_NET_CLS_BASIC is not set ++# CONFIG_NET_CLS_TCINDEX is not set ++# CONFIG_NET_CLS_ROUTE4 is not set ++# CONFIG_NET_CLS_FW is not set ++# CONFIG_NET_CLS_U32 is not set ++# CONFIG_NET_CLS_RSVP is not set ++# CONFIG_NET_CLS_RSVP6 is not set ++# CONFIG_NET_EMATCH is not set ++# CONFIG_NET_CLS_ACT is not set ++# CONFIG_NET_CLS_POLICE is not set ++CONFIG_NET_ESTIMATOR=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_IRDA is not set ++CONFIG_BT=m ++CONFIG_BT_L2CAP=m ++CONFIG_BT_SCO=m ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++ ++# ++# Bluetooth device drivers ++# ++CONFIG_BT_HCIUSB=m ++CONFIG_BT_HCIUSB_SCO=y ++CONFIG_BT_HCIUART=m ++CONFIG_BT_HCIUART_H4=y ++CONFIG_BT_HCIUART_BCSP=y ++CONFIG_BT_HCIBCM203X=m ++CONFIG_BT_HCIBPA10X=m ++CONFIG_BT_HCIBFUSB=m ++CONFIG_BT_HCIDTL1=m ++CONFIG_BT_HCIBT3C=m ++CONFIG_BT_HCIBLUECARD=m ++CONFIG_BT_HCIBTUART=m ++CONFIG_BT_HCIVHCI=m ++# CONFIG_AF_RXRPC is not set ++CONFIG_FIB_RULES=y ++ ++# ++# Wireless ++# ++# CONFIG_CFG80211 is not set ++CONFIG_WIRELESS_EXT=y ++# CONFIG_MAC80211 is not set ++CONFIG_IEEE80211=m ++# CONFIG_IEEE80211_DEBUG is not set ++CONFIG_IEEE80211_CRYPT_WEP=m ++CONFIG_IEEE80211_CRYPT_CCMP=m ++CONFIG_IEEE80211_CRYPT_TKIP=m ++# CONFIG_IEEE80211_SOFTMAC is not set ++# CONFIG_RFKILL is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++CONFIG_FW_LOADER=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++ ++# ++# Connector - unified userspace <-> kernelspace linker ++# ++CONFIG_CONNECTOR=m ++CONFIG_MTD=y ++# CONFIG_MTD_DEBUG is not set ++CONFIG_MTD_CONCAT=y ++CONFIG_MTD_PARTITIONS=y ++# CONFIG_MTD_REDBOOT_PARTS is not set ++# CONFIG_MTD_CMDLINE_PARTS is not set ++# CONFIG_MTD_AFS_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++# CONFIG_MTD_CHAR is not set ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++CONFIG_MTD_CFI=y ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_GEN_PROBE=y ++# CONFIG_MTD_CFI_ADV_OPTIONS is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_CFI_INTELEXT is not set ++CONFIG_MTD_CFI_AMDSTD=y ++# CONFIG_MTD_CFI_STAA is not set ++CONFIG_MTD_CFI_UTIL=y ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++# CONFIG_MTD_XIP is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PHYSMAP is not set ++# CONFIG_MTD_ARM_INTEGRATOR is not set ++# CONFIG_MTD_SHARP_SL is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOC2000 is not set ++# CONFIG_MTD_DOC2001 is not set ++# CONFIG_MTD_DOC2001PLUS is not set ++CONFIG_MTD_NAND=y ++CONFIG_MTD_NAND_VERIFY_WRITE=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++# CONFIG_MTD_NAND_MUSEUM_IDS is not set ++# CONFIG_MTD_NAND_H1900 is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_SHARPSL is not set ++CONFIG_MTD_NAND_BALLOON3=y ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# UBI - Unsorted block images ++# ++# CONFIG_MTD_UBI is not set ++ ++# ++# Parallel port support ++# ++# CONFIG_PARPORT is not set ++ ++# ++# Plug and Play support ++# ++# CONFIG_PNPACPI is not set ++ ++# ++# Block devices ++# ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=m ++CONFIG_BLK_DEV_CRYPTOLOOP=m ++CONFIG_BLK_DEV_NBD=m ++# CONFIG_BLK_DEV_UB is not set ++# CONFIG_BLK_DEV_RAM is not set ++CONFIG_CDROM_PKTCDVD=m ++CONFIG_CDROM_PKTCDVD_BUFFERS=8 ++# CONFIG_CDROM_PKTCDVD_WCACHE is not set ++CONFIG_ATA_OVER_ETH=m ++CONFIG_IDE=m ++CONFIG_BLK_DEV_IDE=m ++ ++# ++# Please see Documentation/ide.txt for help/info on IDE drives ++# ++# CONFIG_BLK_DEV_IDE_SATA is not set ++CONFIG_BLK_DEV_IDEDISK=m ++CONFIG_IDEDISK_MULTI_MODE=y ++CONFIG_BLK_DEV_IDECS=m ++CONFIG_BLK_DEV_IDECD=m ++CONFIG_BLK_DEV_IDETAPE=m ++CONFIG_BLK_DEV_IDEFLOPPY=m ++CONFIG_BLK_DEV_IDESCSI=m ++# CONFIG_IDE_TASK_IOCTL is not set ++CONFIG_IDE_PROC_FS=y ++ ++# ++# IDE chipset support/bugfixes ++# ++# CONFIG_IDE_GENERIC is not set ++# CONFIG_IDEPCI_PCIBUS_ORDER is not set ++# CONFIG_IDE_ARM is not set ++# CONFIG_BLK_DEV_IDEDMA is not set ++# CONFIG_BLK_DEV_HD is not set ++ ++# ++# SCSI device support ++# ++CONFIG_RAID_ATTRS=m ++CONFIG_SCSI=m ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++CONFIG_CHR_DEV_ST=m ++CONFIG_CHR_DEV_OSST=m ++CONFIG_BLK_DEV_SR=m ++# CONFIG_BLK_DEV_SR_VENDOR is not set ++CONFIG_CHR_DEV_SG=m ++# CONFIG_CHR_DEV_SCH is not set ++ ++# ++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs ++# ++# CONFIG_SCSI_MULTI_LUN is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++CONFIG_SCSI_SPI_ATTRS=m ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++ ++# ++# SCSI low-level drivers ++# ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_SCSI_DEBUG is not set ++ ++# ++# PCMCIA SCSI adapter support ++# ++# CONFIG_PCMCIA_AHA152X is not set ++# CONFIG_PCMCIA_FDOMAIN is not set ++# CONFIG_PCMCIA_NINJA_SCSI is not set ++# CONFIG_PCMCIA_QLOGIC is not set ++# CONFIG_PCMCIA_SYM53C500 is not set ++CONFIG_ATA=m ++# CONFIG_ATA_NONSTANDARD is not set ++CONFIG_PATA_PCMCIA=m ++ ++# ++# Multi-device support (RAID and LVM) ++# ++CONFIG_MD=y ++# CONFIG_BLK_DEV_MD is not set ++CONFIG_BLK_DEV_DM=m ++# CONFIG_DM_DEBUG is not set ++# CONFIG_DM_CRYPT is not set ++# CONFIG_DM_SNAPSHOT is not set ++# CONFIG_DM_MIRROR is not set ++# CONFIG_DM_ZERO is not set ++# CONFIG_DM_MULTIPATH is not set ++# CONFIG_DM_DELAY is not set ++ ++# ++# Network device support ++# ++CONFIG_NETDEVICES=y ++CONFIG_DUMMY=m ++CONFIG_BONDING=m ++CONFIG_EQUALIZER=m ++CONFIG_TUN=m ++CONFIG_PHYLIB=m ++ ++# ++# MII PHY device drivers ++# ++CONFIG_MARVELL_PHY=m ++CONFIG_DAVICOM_PHY=m ++CONFIG_QSEMI_PHY=m ++CONFIG_LXT_PHY=m ++CONFIG_CICADA_PHY=m ++CONFIG_VITESSE_PHY=m ++CONFIG_SMSC_PHY=m ++CONFIG_BROADCOM_PHY=m ++CONFIG_FIXED_PHY=m ++CONFIG_FIXED_MII_10_FDX=y ++CONFIG_FIXED_MII_100_FDX=y ++ ++# ++# Ethernet (10 or 100Mbit) ++# ++CONFIG_NET_ETHERNET=y ++CONFIG_MII=m ++CONFIG_SMC91X=m ++CONFIG_DM9000=m ++CONFIG_SMC911X=m ++CONFIG_NETDEV_1000=y ++CONFIG_NETDEV_10000=y ++ ++# ++# Wireless LAN ++# ++# CONFIG_WLAN_PRE80211 is not set ++CONFIG_WLAN_80211=y ++CONFIG_PCMCIA_RAYCS=m ++CONFIG_LIBERTAS=m ++CONFIG_HERMES=m ++CONFIG_ATMEL=m ++CONFIG_AIRO_CS=m ++CONFIG_PCMCIA_WL3501=m ++# CONFIG_USB_ZD1201 is not set ++CONFIG_HOSTAP=m ++# CONFIG_HOSTAP_FIRMWARE is not set ++CONFIG_HOSTAP_CS=m ++ ++# ++# USB Network Adapters ++# ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_USBNET_MII=m ++CONFIG_USB_USBNET=m ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_RNDIS_HOST=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_BELKIN=y ++CONFIG_USB_ARMLINUX=y ++# CONFIG_USB_EPSON2888 is not set ++CONFIG_USB_KC2190=y ++CONFIG_USB_NET_ZAURUS=m ++CONFIG_NET_PCMCIA=y ++CONFIG_PCMCIA_3C589=m ++CONFIG_PCMCIA_3C574=m ++CONFIG_PCMCIA_FMVJ18X=m ++CONFIG_PCMCIA_PCNET=m ++CONFIG_PCMCIA_NMCLAN=m ++CONFIG_PCMCIA_SMC91C92=m ++CONFIG_PCMCIA_XIRC2PS=m ++CONFIG_PCMCIA_AXNET=m ++# CONFIG_WAN is not set ++CONFIG_PPP=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_ASYNC=m ++# CONFIG_PPP_SYNC_TTY is not set ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_MPPE=m ++CONFIG_PPPOE=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_SLHC=m ++CONFIG_SLIP_SMART=y ++# CONFIG_SLIP_MODE_SLIP6 is not set ++# CONFIG_SHAPER is not set ++CONFIG_NETCONSOLE=m ++CONFIG_NETPOLL=y ++# CONFIG_NETPOLL_TRAP is not set ++CONFIG_NET_POLL_CONTROLLER=y ++ ++# ++# ISDN subsystem ++# ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++CONFIG_INPUT_FF_MEMLESS=m ++# CONFIG_INPUT_POLLDEV is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=480 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=640 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_TSDEV=m ++CONFIG_INPUT_TSDEV_SCREEN_X=480 ++CONFIG_INPUT_TSDEV_SCREEN_Y=640 ++CONFIG_INPUT_EVDEV=y ++CONFIG_INPUT_EVBUG=y ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++CONFIG_KEYBOARD_ATKBD=m ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_PXA27x is not set ++CONFIG_KEYBOARD_GPIO=m ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=m ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_LIFEBOOK=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_SERIAL=m ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++CONFIG_INPUT_JOYSTICK=y ++# CONFIG_JOYSTICK_ANALOG is not set ++# CONFIG_JOYSTICK_A3D is not set ++# CONFIG_JOYSTICK_ADI is not set ++# CONFIG_JOYSTICK_COBRA is not set ++# CONFIG_JOYSTICK_GF2K is not set ++# CONFIG_JOYSTICK_GRIP is not set ++# CONFIG_JOYSTICK_GRIP_MP is not set ++# CONFIG_JOYSTICK_GUILLEMOT is not set ++# CONFIG_JOYSTICK_INTERACT is not set ++# CONFIG_JOYSTICK_SIDEWINDER is not set ++# CONFIG_JOYSTICK_TMDC is not set ++# CONFIG_JOYSTICK_IFORCE is not set ++# CONFIG_JOYSTICK_WARRIOR is not set ++# CONFIG_JOYSTICK_MAGELLAN is not set ++# CONFIG_JOYSTICK_SPACEORB is not set ++# CONFIG_JOYSTICK_SPACEBALL is not set ++# CONFIG_JOYSTICK_STINGER is not set ++# CONFIG_JOYSTICK_TWIDJOY is not set ++# CONFIG_JOYSTICK_JOYDUMP is not set ++# CONFIG_JOYSTICK_XPAD is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++CONFIG_TOUCHSCREEN_UCB1400=m ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++CONFIG_INPUT_MISC=y ++# CONFIG_INPUT_ATI_REMOTE is not set ++# CONFIG_INPUT_ATI_REMOTE2 is not set ++# CONFIG_INPUT_KEYSPAN_REMOTE is not set ++# CONFIG_INPUT_POWERMATE is not set ++# CONFIG_INPUT_YEALINK is not set ++CONFIG_INPUT_UINPUT=y ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++CONFIG_SERIO_LIBPS2=m ++# CONFIG_SERIO_RAW is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++CONFIG_SAMOSA=m ++CONFIG_MINIPUG=m ++ ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_PXA=y ++CONFIG_SERIAL_PXA_CONSOLE=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++CONFIG_UNIX98_PTYS=y ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++ ++# ++# IPMI ++# ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_WATCHDOG=y ++# CONFIG_WATCHDOG_NOWAYOUT is not set ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++CONFIG_SA1100_WATCHDOG=m ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_HW_RANDOM=m ++CONFIG_NVRAM=m ++CONFIG_R3964=m ++ ++# ++# PCMCIA character devices ++# ++# CONFIG_SYNCLINK_CS is not set ++# CONFIG_CARDMAN_4000 is not set ++# CONFIG_CARDMAN_4040 is not set ++# CONFIG_RAW_DRIVER is not set ++ ++# ++# TPM devices ++# ++# CONFIG_TCG_TPM is not set ++CONFIG_I2C=m ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_CHARDEV=m ++ ++# ++# I2C Algorithms ++# ++CONFIG_I2C_ALGOBIT=m ++CONFIG_I2C_ALGOPCF=m ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++CONFIG_I2C_GPIO=m ++CONFIG_I2C_PXA=m ++# CONFIG_I2C_PXA_SLAVE is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Miscellaneous I2C Chip support ++# ++CONFIG_SENSORS_DS1337=m ++CONFIG_SENSORS_DS1374=m ++CONFIG_SENSORS_EEPROM=m ++CONFIG_SENSORS_PCF8574=m ++CONFIG_SENSORS_PCA9539=m ++CONFIG_SENSORS_PCF8591=m ++CONFIG_SENSORS_MAX6875=m ++CONFIG_I2C_DEBUG_CORE=y ++CONFIG_I2C_DEBUG_ALGO=y ++CONFIG_I2C_DEBUG_BUS=y ++CONFIG_I2C_DEBUG_CHIP=y ++ ++# ++# SPI support ++# ++# CONFIG_SPI is not set ++# CONFIG_SPI_MASTER is not set ++ ++# ++# Dallas's 1-wire bus ++# ++CONFIG_W1=m ++CONFIG_W1_CON=y ++ ++# ++# 1-wire Bus Masters ++# ++CONFIG_W1_MASTER_DS2490=m ++CONFIG_W1_MASTER_DS2482=m ++# CONFIG_W1_MASTER_DS1WM is not set ++ ++# ++# 1-wire Slaves ++# ++CONFIG_W1_SLAVE_THERM=m ++CONFIG_W1_SLAVE_SMEM=m ++CONFIG_W1_SLAVE_DS2433=m ++# CONFIG_W1_SLAVE_DS2433_CRC is not set ++CONFIG_HWMON=y ++# CONFIG_HWMON_VID is not set ++# CONFIG_SENSORS_ABITUGURU is not set ++# CONFIG_SENSORS_AD7418 is not set ++# CONFIG_SENSORS_ADM1021 is not set ++# CONFIG_SENSORS_ADM1025 is not set ++# CONFIG_SENSORS_ADM1026 is not set ++# CONFIG_SENSORS_ADM1029 is not set ++# CONFIG_SENSORS_ADM1031 is not set ++# CONFIG_SENSORS_ADM9240 is not set ++# CONFIG_SENSORS_ASB100 is not set ++# CONFIG_SENSORS_ATXP1 is not set ++# CONFIG_SENSORS_DS1621 is not set ++# CONFIG_SENSORS_F71805F is not set ++# CONFIG_SENSORS_FSCHER is not set ++# CONFIG_SENSORS_FSCPOS is not set ++# CONFIG_SENSORS_GL518SM is not set ++# CONFIG_SENSORS_GL520SM is not set ++# CONFIG_SENSORS_IT87 is not set ++# CONFIG_SENSORS_LM63 is not set ++# CONFIG_SENSORS_LM75 is not set ++# CONFIG_SENSORS_LM77 is not set ++# CONFIG_SENSORS_LM78 is not set ++# CONFIG_SENSORS_LM80 is not set ++# CONFIG_SENSORS_LM83 is not set ++# CONFIG_SENSORS_LM85 is not set ++# CONFIG_SENSORS_LM87 is not set ++# CONFIG_SENSORS_LM90 is not set ++# CONFIG_SENSORS_LM92 is not set ++# CONFIG_SENSORS_MAX1619 is not set ++# CONFIG_SENSORS_MAX6650 is not set ++# CONFIG_SENSORS_PC87360 is not set ++# CONFIG_SENSORS_PC87427 is not set ++# CONFIG_SENSORS_SMSC47M1 is not set ++# CONFIG_SENSORS_SMSC47M192 is not set ++# CONFIG_SENSORS_SMSC47B397 is not set ++# CONFIG_SENSORS_VT1211 is not set ++# CONFIG_SENSORS_W83781D is not set ++# CONFIG_SENSORS_W83791D is not set ++# CONFIG_SENSORS_W83792D is not set ++# CONFIG_SENSORS_W83793 is not set ++# CONFIG_SENSORS_W83L785TS is not set ++# CONFIG_SENSORS_W83627HF is not set ++# CONFIG_SENSORS_W83627EHF is not set ++# CONFIG_HWMON_DEBUG_CHIP is not set ++ ++# ++# Misc devices ++# ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_SM501 is not set ++ ++# ++# LED devices ++# ++CONFIG_NEW_LEDS=y ++CONFIG_LEDS_CLASS=m ++ ++# ++# LED drivers ++# ++ ++# ++# LED Triggers ++# ++CONFIG_LEDS_TRIGGERS=y ++CONFIG_LEDS_TRIGGER_TIMER=y ++CONFIG_LEDS_TRIGGER_IDE_DISK=y ++CONFIG_LEDS_TRIGGER_HEARTBEAT=y ++ ++# ++# Multimedia devices ++# ++CONFIG_VIDEO_DEV=m ++# CONFIG_VIDEO_V4L1 is not set ++CONFIG_VIDEO_V4L1_COMPAT=y ++CONFIG_VIDEO_V4L2=y ++CONFIG_VIDEO_CAPTURE_DRIVERS=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++CONFIG_VIDEO_HELPER_CHIPS_AUTO=y ++CONFIG_VIDEO_MSP3400=m ++CONFIG_VIDEO_WM8775=m ++CONFIG_VIDEO_SAA711X=m ++CONFIG_VIDEO_CX25840=m ++CONFIG_VIDEO_CX2341X=m ++CONFIG_VIDEO_SAA5246A=m ++CONFIG_VIDEO_SAA5249=m ++CONFIG_V4L_USB_DRIVERS=y ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_PVRUSB2_29XXX=y ++CONFIG_VIDEO_PVRUSB2_24XXX=y ++CONFIG_VIDEO_PVRUSB2_SYSFS=y ++# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set ++CONFIG_VIDEO_USBVISION=m ++CONFIG_USB_SN9C102=m ++CONFIG_USB_ZR364XX=m ++CONFIG_RADIO_ADAPTERS