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From: Patrick Doyle <wpdster@gmail.com>
Date: Thu, 7 Jul 2011 21:40:30 -0400
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Subject: Re: [Balloon] Should SA_SDCLK0 be wiggling on my Balloon board?
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On Wed, Jul 6, 2011 at 11:57 AM, Patrick Doyle <wpdster@gmail.com> wrote:
> Before I go too far down this path, I figured I should just ask the quest=
ion...
>
> The SDCLK<0> output pin on the PXA270 is wired to SA_SDCLK0, which is
> wired to pin Y11 on the FPGA. =A0I would like to run some synchronous
> logic (specifically, a dual clocked FIFO) off of this clock. =A0Right
> now, it doesn't seem to be wiggling. =A0I can think of 2 reasons
> immediately why I might not see it wiggling:
>
> 1) I did something wrong.
>
> 2) It doesn't wiggle unless it is configured to do so, and the default
> kernel doesn't configure it to wiggle.
>
> I'm working on trying to figure out option (1). =A0I thought I should
> ask you folks about option (2).
>
It seems like I need to set the K0FREE bit of the MDREFR register.  I
can do that fairly easily and hackilly by just OR-ing MDREFR_K0FREE
into MDREFR inside a loadable kernel module.

Is there a better (kernel or even user space) API for examining and
manipulating bits in MDREFR and other registers?

--wpd

